 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture - 121 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General-purpose Working Registers + Peripheral Control Registers - Up to 6 MIPS Throughput at 6 MHz Data and Nonvolatile Program Memory - 128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles - 4K Bytes Internal SRAM - 4K Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security - SPI Interface for In-System Programming Peripheral Features - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - Programmable Serial UART - Master/Slave SPI Serial Interface - Real-time Counter (RTC) with Separate Oscillator - Two 8-bit Timer/Counters with Separate Prescaler and PWM - Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM - Programmable Watchdog Timer with On-chip Oscillator - 8-channel, 10-bit ADC Special Microcontroller Features - Low-power Idle, Power-save and Power-down Modes - Software Selectable Clock Frequency - External and Internal Interrupt Sources Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation Power Consumption at 4 MHz, 3V, 25C - Active: 5.5 mA - Idle Mode: 1.6 mA - Power-down Mode: < 1 A I/O and Packages - 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines - 64-lead TQFP Operating Voltages - 2.7 - 3.6V for ATmega103L - 4.0 - 5.5V for ATmega103 Speed Grades - 0 - 4 MHz for ATmega103L - 0 - 6 MHz for ATmega103 * * 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103(L) * * * * * * Rev. 0945G-09/01 1 Pin Configuration PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PC7 (A15) ALE TQFP PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (AD2) PA2 (AD1) PA1 (AD0) PA0 VCC GND (ADC7) PF7 (ADC6) PF6 (ADC5) PF5 (ADC4) PF4 (ADC3) PF3 (ADC2) PF2 (ADC1) PF1 (ADC0) PF0 AREF AGND AVCC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 INDEX CORNER WR 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RD PD7 (T2) PD6 (T1) PD5 PD4 (IC1) PD3 (INT3) PD2 (INT2) PD1 (INT1) PD0 (INT0) XTAL1 XTAL2 GND VCC RESET TOSC1 TOSC2 PB7 (OC2/PWM2) 1 PEN 2 (PDI/RXD) PE0 3 (PDO/TXD) PE1 4 (AC+) PE2 5 (AC-) PE3 6 (INT4) PE4 7 (INT5) PE5 8 (INT6) PE6 9 (INT7) PE7 10 (SS) PB0 11 (SCK) PB1 12 (MOSI) PB2 13 (MISO) PB3 14 (OC0/PWM0) PB4 15 (OC1A/PWM1A) PB5 16 (OC1B/PWM1B) PB6 2 ATmega103(L) 0945G-09/01 ATmega103(L) Description The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega103(L) provides the following features: 128K bytes of In-System Programmable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general-purpose I/O lines, 8 input lines, 8 output lines, 32 general-purpose working registers, real-time counter (RTC), 4 flexible timer/counters with compare modes and PWM, UART, programmable watchdog timer with internal oscillator, an SPI serial port and 3 software-selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel's high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega103(L) AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators and evaluation kits. 3 0945G-09/01 Block Diagram Figure 1. The ATmega103(L) Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 VCC GND PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA BUS PORTA DRIVER/BUFFERS PORTC DRIVERS ANALOG MUX ADC AGND AREF INTERNAL OSCILLATOR OSCILLATOR XTAL1 XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER OSCILLATOR TOSC2 PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMING AND CONTROL TOSC1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS RESET ALE WR RD INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER PROGRAMMING LOGIC PEN SPI UART ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + - VCC PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS GND PE0 - PE7 PB0 - PB7 PD0 - PD7 4 ATmega103(L) 0945G-09/01 ATmega103(L) Pin Descriptions VCC GND Port A (PA7..PA0) Supply voltage. Ground. Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A serves as Multiplexed Address/Data bus when using external SRAM. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated. Port B also serves the functions of various special features. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C (PC7..PC0) Port C is an 8-bit output port. The Port C output buffers can sink 20 mA. Port C also serves as Address output when using external SRAM. Since Port C is an output only port, the Port C pins are not tri-stated when a reset condition becomes active. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running Port F (PF7..PF0) RESET Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC. Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. 5 0945G-09/01 XTAL1 XTAL2 TOSC1 TOSC2 WR RD ALE Input to the inverting Timer/Counter oscillator amplifier. Output from the inverting Timer/Counter oscillator amplifier. External SRAM write strobe External SRAM read strobe ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the second access cycle. Supply voltage for Port F, including ADC. The pin must be connected to VCC when not used for the ADC. See "ADC Noise Canceling Techniques" on page 77 for details when using the ADC. AREF is the analog reference input for the ADC converter. For ADC operations, a voltage in the range AGND to AVCC must be applied to this pin. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND. PEN is a programming enable pin for the serial programming mode. By holding this pin low during a power-on reset, the device will enter the serial programming mode. PEN has no function during normal operation. AVCC AREF AGND PEN Clock Options Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. Figure 2. Oscillator Connections MAX 1 HC BUFFER HC C2 C1 XTAL2 XTAL1 GND Note: When using the MCU oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. 6 ATmega103(L) 0945G-09/01 ATmega103(L) External Clock To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 3. External Clock Drive Configuration NC EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 GND Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the pins. No external capacitors are needed. The oscillator is optimized for use with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not recommended. 7 0945G-09/01 Architectural Overview Figure 4. The ATmega103(L) AVR RISC Architecture AVR ATmega103(L) Architecture Data Bus 8-bit 64K x 16 Program Memory Program Counter Status and Test Instruction Register 32 x 8 General Purpose Registers Peripherals Indirect Addressing Direct Addressing Instruction Decoder ALU Control Lines 4K x 8 Data SRAM 4K x 8 EEPROM The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is accessed with a single-level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM and, consequently, the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer (SP) is read/write accessible in the I/O space. The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa- 8 ATmega103(L) 0945G-09/01 ATmega103(L) r a te i nt er r up t v e c to r i n t h e i n te r r u pt v ec t or t a bl e at th e b e gi n ni n g of th e program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps. General-purpose Register File Figure 5 shows the structure of the 32 general-purpose working registers in the CPU. Figure 5. AVR CPU General-purpose Working Registers 7 R0 R1 R2 .=.=. R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X-register low byte X-register high byte Y-register low byte Y-register high byte Z-register low byte Z-register high byte $0D $0E $0F $10 $11 0 Addr. $00 $01 $02 All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two registers or on a single register apply to the entire register file. As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. The 4K bytes of SRAM available for general data are implemented as addresses $0060 to $0FFF. 9 0945G-09/01 X-register, Y-register and Zregister The registers R26..R31 have some added functions to their general-purpose usage. These registers are address pointers for indirect addressing of the SRAM. The three indirect address registers X, Y, and Z are defined as: Figure 6. X-, Y-, and Z-registers 15 X-register 7 R27 ($1B) 0 7 R26 ($1A) 0 0 15 Y-register 7 R29 ($1D) 15 Z-register 7 R31 ($1F) 0 7 R30 ($1E) 0 0 7 R28 ($1C) 0 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories: arithmetic, logical and bit functions. The ATmega103(L) contains 128K bytes of On-chip In-System Programmable Flash memory for program storage. Since all instructions are single or double 16-bit words, the Flash is organized as 64K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. Constant tables can be allocated in the entire program memory space (see the LPM - Load Program Memory and ELPM - Extended Load Program Memory instruction descriptions). ISP Flash Program Memory SRAM Data Memory The ATmega103(L) supports two different configurations for the SRAM data memory as listed in Table 1. Table 1. Memory Configurations Configuration A B Note: Internal SRAM Data Memory 4000 4000 External SRAM Data Memory None up to 64K When using 64K of external SRAM, 60K will be available. 10 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 7. Memory Configurations Memory Configuration A Program Memory $0000 Data Memory 32 Registers 64 I/O Registers Internal SRAM (4000 x 8) $0FFF $0000 - $001F $0020 - $005F $0060 Program Flash (32K/64K x 16) $7FFF/$FFFF Memory Configuration B Program Memory $0000 Data Memory 32 Registers 64 I/O Registers Internal SRAM (4000 x 8) $0000 - $001F $0020 - $005F $0060 $0FFF $1000 Program Flash (32K/64K x 16) External SRAM (0 - 64K x 8) $7FFF/ $FFFF $FFFF 11 0945G-09/01 The 4096 first data memory locations address both the register file, the I/O memory and the internal data SRAM. The first 96 locations address the register file and I/O memory, and the next 4000 locations address the internal data SRAM. An optional external data SRAM can be used with the ATmega103(L). This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of the external memory is lost as the addresses are occupied by internal memory. When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR register. Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the 2-byte program counter is pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles are used per byte. This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns will need four clock cycles more than specified in the "Instruction Set Summary" on page 130. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented. The entire data address space including the 32 general-purpose working registers and the 64 I/O registers are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The ATmega103(L) AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, register file and I/O memory). This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. 12 ATmega103(L) 0945G-09/01 ATmega103(L) Register Direct, Single Register Rd Figure 8. Direct Single Register Addressing REGISTER FILE 0 15 OP 4 d 0 d 31 The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Figure 9. Direct Register Addressing, Two Registers REGISTER FILE 0 15 OP 9 r 54 d 0 d r 31 Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 10. I/O Direct Addressing I/O MEMORY 0 15 OP n 5 P 0 63 Operand address is contained in six bits of the instruction word. n is the destination or source register address. 13 0945G-09/01 Data Direct Figure 11. Direct Data Addressing Data Space 31 OP 16 LSBs 15 0 20 19 Rr/Rd 16 $0000 $FFFF A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Figure 12. Data Indirect with Displacement Data Space $0000 15 Y- OR Z-REGISTER 0 15 OP 10 n 65 a 0 $FFFF Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word. Data Indirect Figure 13. Data Indirect Addressing Data Space $0000 15 X-, Y- OR Z-REGISTER 0 $FFFF Operand address is the contents of the X-, Y,- or the Z-register. 14 ATmega103(L) 0945G-09/01 ATmega103(L) Data Indirect with Predecrement Figure 14. Data Indirect Addressing with Pre-decrement Data Space $0000 15 X-, Y- OR Z-REGISTER 0 -1 $FFFF The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Data Indirect with Postincrement Figure 15. Data Indirect Addressing with Post-increment Data Space $0000 15 X-, Y- OR Z-REGISTER 0 1 $FFFF The X-, Y-, or the Z-register is incremented after the operation. Operand address is the contents of the X-, Y-, or the Z-register prior to incrementing. Constant Addressing Using the LPM and ELPM Instructions Figure 16. Code Memory Constant Addressing PROGRAM MEMORY $0000 15 Z-REGISTER 10 $7FFF/$FFFF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 32K), LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). 15 0945G-09/01 If ELPM is used, LSB of the RAM Page Z register (RAMPZ) is used to select low or high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page). Direct Program Address, JMP and CALL Figure 17. Direct Program Memory Addressing PROGRAM MEMORY $0000 31 OP 16 LSBs 15 0 21 20 16 $7FFF/$FFFF Program execution continues at the address immediate in the instruction words. Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing PROGRAM MEMORY $0000 15 Z-REGISTER 0 $7FFF/$FFFF Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing PROGRAM MEMORY $0000 15 PC 0 1 15 OP 12 11 k $7FFF/$FFFF 0 16 ATmega103(L) 0945G-09/01 ATmega103(L) Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. EEPROM Data Memory The EEPROM memory is organized as a separate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 54 specifying the EEPROM address register, the EEPROM data register and the EEPROM control register. This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock O, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit. Figure 20. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 Memory Access Times and Instruction Execution Timing System Clock O 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 21. Single Cycle ALU Operation T1 T2 T3 T4 System Clock O Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 17 0945G-09/01 The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22. On-chip Data SRAM Access Cycles T1 T2 T3 T4 System Clock O Address Data WR Data RD Prev. Address Address See "Interface to External SRAM" on page 79. for a description of the access to the external SRAM. I/O Memory The I/O space definition of the ATmega103(L) is shown in Table 2. Table 2. ATmega103(L) I/O Space I/O Address (SRAM Address) $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) Name SREG SPH SPL XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B Function Status REGister Stack Pointer High Stack Pointer Low XTAL Divide Control Register RAM Page Z Select Register External Interrupt Control Register External Interrupt MaSK register External Interrupt Flag Register Timer/Counter Interrupt MaSK register Timer/Counter Interrupt Flag register MCU General Control Register MCU Status Register Timer/Counter0 Control Register Timer/Counter0 (8-bit) Timer/Counter0 Output Compare Register Asynchronous Mode Status Register Timer/Counter1 Control Register A Timer/Counter1 Control Register B 18 ATmega103(L) 0945G-09/01 Read Write ATmega103(L) Table 2. ATmega103(L) I/O Space (Continued) I/O Address (SRAM Address) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $21 ($41) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) Name TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR ADMUX Function Timer/Counter1 High Byte Timer/Counter1 Low Byte Timer/Counter1 Output Compare Register A High Byte Timer/Counter1 Output Compare Register A Low Byte Timer/Counter1 Output Compare Register B High Byte Timer/Counter1 Output Compare Register B Low Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Low Byte Timer/Counter2 Control Register Timer/Counter2 (8-bit) Timer/Counter2 Output Compare Register Watchdog Timer Control Register EEPROM Address Register High EERPOM Address Register Low EEPROM Data Register EEPROM Control Register Data Register, Port A Data Direction Register, Port A Input Pins, Port A Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port C Data Register, Port D Data Direction Register, Port D Input Pins, Port D SPI I/O Data Register SPI Status Register SPI Control Register UART I/O Data Register UART Status Register UART Control Register UART Baud Rate Register Analog Comparator Control and Status Register ADC Multiplexer Select Register 19 0945G-09/01 Table 2. ATmega103(L) I/O Space (Continued) I/O Address (SRAM Address) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) Note: Name ADCSR ADCH ADCL PORTE DDRE PINE Function ADC Control and Status Register ADC Data Register High ADC Data Register Low Data Register, Port E Data Direction Register, Port E Input Pins, Port E $00 ($20) PINF Input Pins, Port F Reserved and unused locations are not shown in the table. All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The different I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the "Instruction Set Summary" on page 130 for more details. When using the I/O specific instructions IN and OUT, the I/O register address $00 - $3F are used. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The different I/O and peripherals control registers are explained in the following sections. Status Register - SREG The AVR status register (SREG) at I/O space location $3F ($5F) is defined as: Bit $3F ($5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts. * Bit 6 - T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied 20 ATmega103(L) 0945G-09/01 ATmega103(L) into T by the BST instruction and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. * Bit 5 - H: Half-carry Flag The half-carry flag H indicates a half-carry in some arithmetic operations. See the instruction set description on page 130 for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the instruction set description on page 130 for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the instruction set description on page 130 for detailed information. * Bit 2 - N: Negative Flag The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction set description on page 130 for detailed information. * Bit 1 - Z: Zero Flag The zero flag Z indicates a zero result from an arithmetical or logical operation. See the instruction set description on page 130 for detailed information. * Bit 0 - C: Carry Flag The carry flag C indicates a carry in an arithmetical or logical operation. See the instruction set description on page 130 for detailed information. Note that the status register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software. Stack Pointer - SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega103(L) supports up to 64K bytes memory, all 16 bits are used. Bit $3E ($5E) $3D ($5D) Read/Write Initial Value 15 SP15 SP7 7 R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the stack with the PUSH instruction and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI. 21 0945G-09/01 RAM Page Z Select Register - RAMPZ Bit $3B ($5B) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 RAMPZ0 R/W 0 RAMPZ The RAMPZ register is normally used to select which 64K RAM page is accessed by the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: RAMPZ0 = 0: RAMPZ0 = 1: Program memory address $0000 - $7FFF (lower 64K bytes) is accessed by ELPM Program memory address $8000 - $FFFF (higher 64K bytes) is accessed by ELPM Note that LPM is not affected by the RAMPZ setting. MCU Control Register - MCUCR The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) Read/Write Initial Value 7 SRE R/W 0 6 SRW R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 - R 0 1 - R 0 0 - R 0 MCUCR * Bit 7 - SRE: External SRAM Enable When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings in the respective data direction registers. When the SRE bit is cleared (zero), the external data SRAM is disabled and the normal pin and data direction settings are used. * Bit 6 - SRW: External SRAM Wait State When the SRW bit is set (one), a one-cycle wait state is inserted in the external data SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM access is executed with a three-cycle scheme. See Figure 51 on page 80 and Figure 52 on page 80. * Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmer's purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. * Bits 4, 3 - SM1/SM0: Sleep Mode Select Bits 1 and 0 This bit selects between the three available sleep modes as shown in Table 3. Table 3. Sleep Mode Select SM1 0 0 1 1 SM0 0 1 0 1 Sleep Mode Idle Mode Reserved Power-down Power-save 22 ATmega103(L) 0945G-09/01 ATmega103(L) * Bits 2..0 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. XTAL Divide Control Register - XDIV The XTAL Divide Control Register is used to divide the XTAL clock frequency by a number in the range 1 - 129. This feature can be used to decrease power consumption when the requirement for processing power is low. Bit $3C ($5C) Read/Write Initial Value 7 XDIVEN R/W 0 6 XDIV6 R/W 0 5 XDIV5 R/W 0 4 XDIV4 R/W 0 3 XDIV3 R/W 0 2 XDIV2 R/W 0 1 XDIV1 R/W 0 0 XDIV0 R/W 0 XDIV * Bit 7 - XDIVEN: XTAL Divide Enable When the XDIVEN bit is set (one), the clock frequency of the CPU and all peripherals is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be set and cleared run-time to vary the clock frequency as suitable to the application. * Bits 6..0 - XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0 These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of these bits is denoted d, the following formula defines the resulting CPU clock frequency fclk: XTAL f CLK = -----------------129 - d The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is set to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When XDIVEN is cleared to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the speed of all peripherals is reduced when a division factor is used. Reset and Interrupt Handling The ATmega103(L) provides 23 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 4. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority and next is INT0 (the External Interrupt Request 0), etc. Table 4. Reset and Interrupt Vectors Vector No. 1 2 3 4 5 6 Program Address $0000 $0002 $0004 $0006 $0008 $000A Source RESET INT0 INT1 INT2 INT3 INT4 Interrupt Definition Hardware Pin, Power-on Reset and Watchdog Reset External Interrupt Request 0 External Interrupt Request 1 External Interrupt Request 2 External Interrupt Request 3 External Interrupt Request 4 23 0945G-09/01 Table 4. Reset and Interrupt Vectors (Continued) Vector No. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Program Address $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E Source INT5 INT6 INT7 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC UART, RX UART, UDRE UART, TX ADC EE READY ANALOG COMP Interrupt Definition External Interrupt Request 5 External Interrupt Request 6 External Interrupt Request 7 Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match Timer/Counter0 Overflow SPI Serial Transfer Complete UART, Rx Complete UART Data Register Empty UART, Tx Complete ADC Conversion Complete EEPROM Ready Analog Comparator The most typical program setup for the Reset and Interrupt vector addresses are: Address Labels Code $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET EXT_INT0 EXT_INT1 EXT_INT2 EXT_INT3 EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC UART_RXC UART_DRE Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ; IRQ2 Handler ; IRQ3 Handler ; IRQ4 Handler ; IRQ5 Handler ; IRQ6 Handler ; IRQ7 Handler ; Timer2 Compare Handler ; Timer2 Overflow Handler ; Timer1 Capture Handler ; Timer1 CompareA Handler ; Timer1 CompareB Handler ; Timer1 Overflow Handler ; Timer0 Compare Handler ; Timer0 Overflow Handler ; SPI Transfer Complete Handler ; UART RX Complete Handler ; UDR Empty Handler 24 ATmega103(L) 0945G-09/01 ATmega103(L) $0028 $002A $002C $002E ; $0030 $0031 $0032 $0033 $0034 ... ... MAIN: ldi out ldi out ... Reset Sources The ATmega103(L) has three sources of reset: * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. During reset, all I/O registers except the MCU Status Register are then set to their initial values and the program starts execution from address $0000. The instruction placed in address $0000 must be a JMP (absolute jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 5 defines the timing and electrical parameters of the reset circuitry. Figure 23. Reset Logic VCC Power-on Reset Circuit POR RESET 100-500K 10-50K Reset Circuit S Q COUNTER RESET PEN D E Q Watchdog Timer SUT0 SUT1 On-chip RC Oscillator 14-stage Ripple Counter Q8 Q11 Q13 R Q XTAL1 Delay Unit 0945G-09/01 INTERNAL RESET 25 Table 5. Reset Characteristics (VCC = 5.0V) Symbol Parameter Power-on Reset Threshold (rising) Power-on Reset Threshold (falling) RESET Pin Threshold Voltage SUT = 00 TTOUT Reset Delay Time-out Period SUT = 01 SUT = 10 SUT = 11 0.4 3.2 12.8 Condition Min 1.0 0.4 Typ 1.4 0.6 VCC/2 5 0.5 4.0 16.0 0.6 4.8 19.2 Max 1.8 0.8 Units V V V CPU cycles ms VPOT(1) VRST Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Poweron Threshold voltage (VPOT), regardless of the VCC rise time (see Figure 24). The Fuse bits SUT1 and SUT0 are used to select start-up time as indicated in Table 5. A "0" in the table indicates that the fuse is programmed. The user can select the start-up time according to typical oscillator start-up time. The number of WDT oscillator cycles used for each time-out except for SUT = 00 is shown in Table 6. The frequency of the Watchdog oscillator is voltage-dependent as shown in "Typical Characteristics" on page 118. Table 6. Number of Watchdog Oscillator Cycles SUT 1/0 01 10 11 Time-out at VCC = 5V 0.5 ms 4.0 ms 16.0 ms Number of WDT Cycles 512 4K 16K The setting SUT 1/0 = 00 starts the MCU after 5 CPU clock cycles, and can be used when an external clock signal is applied to the XTAL1 pin. This setting does not use the WDT oscillator and enables very fast start-up from the sleep modes Power-down or Power-save if the clock signal is present during sleep. For details, refer to the programming specification starting on page 99. If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the pin low for a period after V CC has been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing example of this. 26 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 24. MCU Start-up, RESET Tied to VCC. VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 25. MCU Start-up, RESET Controlled Externally VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired. Figure 26. External Reset during Operation VCC RESET VRST TIME-OUT tTOUT INTERNAL RESET 27 0945G-09/01 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 52 for details on operation of the Watchdog. Figure 27. Watchdog Reset during Operation VCC RESET WDT TIME-OUT 1 XTAL Cycle RESET TIME-OUT INTERNAL RESET tTOUT MCU Status Register - MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit $34 ($54) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 EXTRF R/W 0 PORF R/W MCUSR See bit description * Bits 7..2 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. * Bit 1 - EXTRF: External Reset Flag After a Power-on Reset, this bit is undefined (X). It will be set by an external reset. A Watchdog reset will leave this bit unchanged. * Bit 0 - PORF: Power-on Reset Flag This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave this bit unchanged. To summarize, Table 7 shows the value of these two bits after the three modes of reset: Table 7. PORF and EXTRF Values after Reset Reset Source Power-on Reset External Reset Watchdog Reset EXTRF undefined 1 unchanged PORF 1 unchanged unchanged To make use of these bits to identify a reset condition, the user software should clear both the PORF and EXTRF bits as early as possible in the program. Checking the PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before an external or Watchdog reset occurs, the source of reset can be found by using the following truth table, Table 8. 28 ATmega103(L) 0945G-09/01 ATmega103(L) Table 8. Reset Source Identification Reset Source Watchdog Reset Power-on Reset External Reset Power-on Reset EXTRF 0 0 1 1 PORF 0 1 0 1 Interrupt Handling The ATmega103(L) has two dedicated 8-bit Interrupt Mask control registers; EIMSK (External Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). In addition, other enable and mask bits can be found in the peripheral control registers. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed. When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical "1" to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software. If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active. Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software. External Interrupt Mask Register - EIMSK Bit $39 ($59) Read/Write Initial Value 7 INT7 R/W 0 6 INT6 R/W 0 5 INT5 R/W 0 4 INT4 R/W 0 3 INT3 R/W 0 2 INT2 R/W 0 1 INT1 R/W 0 0 INT0 R/W 0 EIMSK * Bits 7..4 - INT7 - INT4: External Interrupt Request 7 - 4 Enable When an INT7 - INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register (EICR) define whether the external interrupt is activated on rising or falling edge or is level-sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. * Bits 3..0 - INT3 - INT0: External Interrupt Request 3 - 0 Enable When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The external interrupts are always low-level triggered interrupts. Activity on any of these pins will trigger an interrupt 29 0945G-09/01 request even if the pin is enabled as an output. This provides a way of generating a software interrupt. When enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. External Interrupt Flag Register - EIFR Bit $38 ($58) Read/Write Initial Value 7 INTF7 R/W 0 6 INTF6 R/W 0 5 INTF5 R/W 0 4 INTF4 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 EIFR * Bits 7..4 - INTF7 - INTF4: External Interrupt 7 - 4 Flags When an edge on the INT7 - INT4 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF4, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT4 in EIMSK, is set (one), the MCU will jump to the interrupt vector. The flag is cleared when the corresponding interrupt routine is executed. Alternatively, the flag is cleared by writing a logical "1" to it. These flags are always cleared when INTF7 - INFT4 are configured as level interrupts. * Bits 3..0 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. External Interrupt Control Register - EICR Bit $3A ($5A) Read/Write Initial Value 7 ISC71 R/W 0 6 ISC70 R/W 0 5 ISC61 R/W 0 4 ISC60 R/W 0 3 ISC51 R/W 0 2 ISC50 R/W 0 1 ISC41 R/W 0 0 ISC40 R/W 0 EICR * Bits 7..0 - ISCX1, ISCX0: External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK are set. The level and edges on the external pins that activate the interrupts are defined in Table 9. Table 9. Interrupt Sense Control ISCX1 0 0 1 1 ISCX0 0 1 0 1 Description The low level of INTX generates an interrupt request. Reserved The falling edge of INTX generates an interrupt request. The rising edge of INTX generates an interrupt request. The value on the INTX pin is sampled before detecting edges. If edge interrupt is selected, pulses that last longer than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. 30 ATmega103(L) 0945G-09/01 ATmega103(L) Timer/Counter Interrupt Mask Register - TIMSK Bit $37 ($57) Read/Write Initial Value 7 OCIE2 6 TOIE2 5 TICIE1 4 OCIE1A 3 OCIE1B 2 TOIE1 1 OCIE0 0 TOIE0 TIMSK R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bit 7 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $0012) is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). * Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register. * Bit 4 - OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $0018) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register. * Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register. * Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register. * Bit 1 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register. * Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register. 31 0945G-09/01 Timer/Counter Interrupt Flag Register - TIFR Bit $36 ($56) Read/Write Initial Value 7 OCF2 R/W 0 6 TOV2 R/W 0 5 ICF1 R/W 0 4 OCF1A R/W 0 3 OCF1B R/W 0 2 TOV1 R/W 0 1 OCF0 R/W 0 0 TOV0 R/W 0 TIFR * Bit 7 - OCF2: Output Compare Flag 2: The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data in OCR2 - Output Compare Register 2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logical "1" to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output Compare interrupt is executed. * Bit 6 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logical "1" to the flag. When the I-bit in SREG, and TOIE2 (Ti mer /Counter 1 O v erfl ow Inte rr upt Enabl e) and TOV 2 ar e s et ( one ), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00. * Bit 5 - ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical "1" to the flag. When the SREG I-bit, TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture interrupt is executed. * Bit 4 - OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical "1" to the flag. When the I-bit in SREG and OCIE1A (Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the Timer/Counter1 CompareA Match interrupt is executed. * Bit 3 - OCF1B: Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logical "1" to the flag. When the I-bit in SREG and OCIE1B (Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the Timer/Counter1 CompareB Match interrupt is executed. * Bit 2 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical "1" to the flag. When the I-bit in SREG and TOIE1 (Ti mer /Counter 1 O v erfl ow Inte rr upt Enabl e) and TOV 1 ar e s et ( one ), the Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000. 32 ATmega103(L) 0945G-09/01 ATmega103(L) * Bit 1 - OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in OCR0 - Output Compare Register 0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logical "1" to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter2 Compare Interrupt Enable) and the OCF0 are set (one), the Timer/Counter0 Output Compare interrupt is executed. * Bit 0 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical "1" to the flag. When the SREG I-bit and TOIE0 (Ti mer /Counter 0 O v erfl ow Inte rr upt Enabl e) and TOV 0 ar e s et ( one ), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this four-clock-cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the stack, and the Stack Pointer is incremented by 2. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Sleep Modes To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR register select which sleep mode (Idle, Power-down, or Power-save) will be activated by the SLEEP instruction, see Table 3 on page 22. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM, and I/O memory are unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector. Idle Mode When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle mode. When the MCU wakes up from Idle mode, the CPU starts program execution immediately. When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down mode. In this mode, the external oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog reset (if enabled), or an external level interrupt can wake up the MCU. Power-down Mode 33 0945G-09/01 Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog oscillator clock and if the input has the required level during this time, the MCU will wake up. The period of the Watchdog oscillator is 1 s (nominal) at 5.0V and 25C. The frequency of the Watchdog oscillator is voltage-dependent, as shown in "Typical Characteristics" on page 118. When waking up from Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same SUT fuses that define the reset time-out period. The wake-up period is equal to the clock reset period, as shown in Table 5 on page 26. If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be executed. Power-save Mode When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. In addition to the Power-down wake-up sources, the device can also wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK. To ensure that the part executes the interrupt routine when waking up, also set the global interrupt enable bit i SREG. When waking up from Power-save mode by an external interrupt, two instruction cycles are executed before the interrupt flags are updated. When waking up by the asynchronous timer, three instruction cycles are executed before the flags are updated. During these cycles, the processor executes instructions, but the interrupt condition is not readable and the interrupt routine has not started yet. If the asynchronous timer is not clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS0 is 0. 34 ATmega103(L) 0945G-09/01 ATmega103(L) Timer/Counters The ATmega103(L) provides three general-purpose Timer/Counters - two 8-bit T/Cs and one 16-bit T/C. Timer/Counter0 optionally can be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz crystal, enabling use of Timer/Counter0 as a Real-time Clock (RTC). Timer/Counter0 has its own prescaler. Timer/Counters 1 and 2 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection that triggers the counting. Figure 28. Prescaler for Timer/Counter1 and Timer/Counter2 CK 10-BIT T/C PRESCALER Timer/Counter Prescalers CK/256 CK/64 T1 T2 0 0 CS20 CS21 CS22 CS10 CS11 CS12 TIMER/COUNTER2 CLOCK SOURCE TCK2 TIMER/COUNTER1 CLOCK SOURCE TCK1 For Timer/Counters 1 and 2, the CK/256 and CK/1024, where CK can be lower than the XTAL Timer/Counters 1 and 2, added selected as clock sources. four different prescaled selections are: CK/8, CK/64, is the CPU clock. Observe that CPU clock frequency frequency if the XTAL div ider is enabled. For selections as CK, external source and stop can be Figure 29. The Timer/Counter0 Prescaler CK TOSC1 PCK0 10-BIT T/C PRESCALER PCK0/32 PCK0/128 PCK0/8 PCK0/64 PCK0/256 PCK0/1024 AS0 CS00 CS01 CS02 TIMER/COUNTER0 CLOCK SOURCE PCK0 CK/1024 CK/8 35 0945G-09/01 The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default connected to the main system clock CK. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. By setting the AS0 bit in ASSR, Timer/Counter0 prescaler is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real-time Clock (RTC). A crystal can be connected between the TOSC1 and TO SC2 pins to ser ve as an independent clock sourc e for Timer/Counter0. This oscillator is optimized for use with a 32.768 kHz crystal. 8-bit Timer/Counters T/C0 and T/C2 Figure 30 shows the block diagram for Timer/Counter0. Figure 31 shows the block diagram for Timer/Counter2. Figure 30. Timer/Counter0 Block Diagram T/C0 OVER- T/C0 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 8-BIT ASYNCH T/C0 DATA BUS OCIE1B TICIE1 OCIE2 OCIE1A OCIE0 TOIE2 TOIE1 TOIE0 OCF0 TOV0 TIMER INT. MASK REGISTER (TIMSK) OCF2 TIMER INT. FLAG REGISTER (TIFR) ICF1 OCF2B OCF2A OCF0 TOV2 TOV1 TOV0 T/C0 CONTROL REGISTER (TCCR0) CS02 CS01 COM01 COM00 PWM0 CTC0 CS00 7 TIMER/COUNTER0 (TCNT0) 0 T/C CLEAR T/C CLK SOURCE UP/DOWN CONTROL LOGIC PCK0 7 8-BIT COMPARATOR 0 7 OUTPUT COMPARE REGISTER0 (OCR0) 0 ASYNCH. STATUS REGISTER (ASSR) AS0 OCR0UB ICR0UB TC0UB CK TCK0 SYNCH UNIT 36 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 31. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS TICIE1 OCIE1B OCIE1A OCIE2 OCIE0 TOIE2 TOIE1 TOIE0 OCF2 TIMER INT. MASK REGISTER (TIMSK) OCF2 TOV2 TIMER INT. FLAG REGISTER (TIFR) ICF1 OCF2B OCF2A OCF0 TOV2 TOV1 TOV0 T/C2 CONTROL REGISTER (TCCR2) CS22 CS21 COM21 COM20 PWM2 CTC2 CS20 7 TIMER/COUNTER2 (TCNT2) 0 T/C CLEAR T/C CLK SOURCE UP/DOWN CK CONTROL LOGIC T2 7 8-BIT COMPARATOR 0 7 OUTPUT COMPARE REGISTER2 (OCR2) 0 The 8-bit Timer/Counter0 can select clock source from PCK0 or prescaled PCK0. The 8bit Timer/Counter2 can select clock source from CK, prescaled CK or an external pin. Both Timer/Counters can be stopped as described in the specification for the Timer/Counter Control Registers - TCCR0 and TCCR2. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter Control Registers - TCCR0 and TCCR2. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counters feature a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make these units useful for lower speed functions or exact timing functions with infrequent actions. Both Timer/Counters support two Output Compare functions using the output compare registers (OCR0 and OCR2) as the data source to be compared to the Timer/Counter contents. The Output Compare functions include optional clearing of the counter on compare match and action on the output compare pins - PB4(OC0/PWM0) and PB7(OC2/PWM2) - on compare match. Timer/Counters 0 and 2 can also be used as 8-bit Pulse Width Modulators. In this mode the Timer/Counter and the output compare register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 40 for a detailed description of this function. 37 0945G-09/01 Timer/Counter0 Control Register - TCCR0 Bit 33 ($53) Read/Write Initial Value 7 - R 0 6 PWM0 R/W 0 5 COM01 R/W 0 4 COM00 R/W 0 3 CTC0 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 Timer/Counter2 Control Register - TCCR2 Bit $25 ($45) Read/Write Initial Value 7 - R 0 6 PWM2 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 CTC2 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2 * Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATmega103(L) and always reads as zero. * Bit 6 - PWM0/PWM2: Pulse Width Modulator Enable When set (one), this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on page 40. * Bits 5, 4 - COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0 The COMn1 and COMn0 control bits determine any output pin action following a compare match in Timer/Counter2. Any output pin actions affect pins PB4 (OC0/PWM0) or PB7 (OC2/PWM2). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. Table 10. Compare Mode Select COMn1 0 0 1 1 Note: COMn0 0 1 0 1 Description Timer/Counter disconnected from output pin OCn/PWMn Toggle the OCn/PWMn output line. Clear the OCn/PWMn output line (to zero). Set the OCn/PWMn output line (to one). n = 0 or 2 In PWM mode, these bits have a different function. Refer to Table 13 for a detailed description. * Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match When the CTC0 or CTC2 control bit is set (one), the Timer/Counter is reset to $00 in the CPU clock cycle after a compare match. If the control bit is cleared, the timer continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used and the compare register is set to C, the timer will count as follows if CTC0/2 is set: ... | C-2 | C-1 | C | 0 | 1 | ... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ... In PWM mode, this bit has no effect. 38 ATmega103(L) 0945G-09/01 ATmega103(L) * Bits 2, 1, 0 - CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits 2, 1 and 0 The Clock Select2 bits 2, 1 and 0 define the prescaling source of the Timer/Counter. Table 11. Timer/Counter0 Prescale Select CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Timer/Counter0 is stopped. PCK0 PCK0/8 PCK0/32 PCK0/64 PCK0/128 PCK0/256 PCK0/1024 Table 12. Timer/Counter2 Prescale Select CS22 0 0 0 0 1 1 1 1 CS21 0 0 1 1 0 0 1 1 CS20 0 1 0 1 0 1 0 1 Description Timer/Counter2 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin PD7(T2), falling edge External Pin PD7(T2), rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK CPU clock. If the external pin modes are used for Timer/Counter2, transitions on PD7/(T2) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer/Counter0 - TCNT0 Bit $32 ($42) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0 Timer/Counter2 - TCNT2 Bit $24 ($44) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT2 These 8-bit registers contain the value of the Timer/Counters. 39 0945G-09/01 Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read and write access. If the Timer/Counter is written to and a clock source is selected, it continues counting in the timer clock cycle after it is preset with the written value. Timer/Counter0 Output Compare Register - OCR0 Bit $31 ($51) Read/Write Initial Value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 OCR0 Timer/Counter2 Output Compare Register - OCR2 Bit $23 ($43) Read/Write Initial Value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 OCR2 The Output Compare registers are 8-bit read/write registers. The Timer/Counter Output Compare Registers contain the data to be continuously compared with the Timer/Counter. Actions on compare matches are specified in TCCR0 and TCCR2. A compare match does only occur if the Timer/Counter counts to the OCR value. A software write that sets the Timer/Counter and Output Compare Register to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counters 0 and 2 in PWM Mode When the PWM mode is selected, the Timer/Counter and the Output Compare Register (OCR0 or OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin. The Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the Output Compare register, the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin is set or cleared according to the settings of the COM01/COM00 or COM21/COM20 bits in the Timer/Counter Control registers TCCR0 and TCCR2. Refer to Table 13 for details. Table 13. Compare Mode Select in PWM Mode COMn1 0 0 1 1 Note: COMn0 0 1 0 1 n = 0 or 2 Effect on Compare/PWM Pin Not connected Not connected Cleared on compare match, up-counting. Set on compare match, downcounting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match, upcounting (inverted PWM). Note that in PWM mode, the Output Compare register is transferred to a temporary location when written. The value is latched when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR0 or OCR2 write. See Figure 32 for an example. 40 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 32. Effects on Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output Synchronized OCR Latch Compare Value changes Counter Value Compare Value PWM Output Unsynchronized OCR Latch Glitch During the time between the write and the latch operation, a read from OCR0 or OCR2 will read the contents of the temporary location. This means that the most recently written value always will read out of OCR0/2. When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM output changes to low or high immediately according to the settings of COM21/COM20 or COM11/COM10. This is shown in Table 14. Table 14. PWM Outputs OCRn = $00 or $FF COMn1 1 1 1 1 Note: n = 0 or 2 COMn0 0 0 1 1 OCRn $00 $FF $00 $FF Output PWMn L H H L In PWM mode, the Timer Overflow flag, TOV0 or TOV2, is set when the counter advances from $00. Timer Overflow Interrupts 0 and 2 operate exactly as in normal Timer/Counter mode, i.e., it is executed when TOV0 or TOV2 is set, provided that Timer Overflow interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts. The frequency of the PWM will be Timer Clock Frequency divided by 510. Asynchronous Status Register - ASSR Bit $30 ($50) Read/Write Initial Value 7 - 6 - 5 - 4 - 3 AS0 2 TCN0UB 1 OCR0UB 0 TCR0UB ASSR R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. 41 0945G-09/01 * Bit 3 - AS0: Asynchronous Timer/Counter0 When set (one), Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero), Timer/Counter0 is clocked from the internal system clock, CK. When the value of this bit is changed, the contents of TCNT0 might get corrupted. * Bit 2 - TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set (one). When TCNT0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical "0" in this bit indicates that TCNT0 is ready to be updated with a new value. * Bit 1 - OCR0UB: Output Compare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set (one). When OCR0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical "0" in this bit indicates that OCR0 is ready to be updated with a new value. * Bit 0 - TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set (one). When TCCR0 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical "0" in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read. Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates synchronously, all operations and timing are identical to Timer/Counter2. During asynchronous operation, however, some considerations must be taken. * WARNING: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers TCNT0, OCR0 and TCCR0 might get corrupted. The following is the safe procedure for switching clock source: 1. Disable the timer 0 interrupts OCIE0 and TOIE0. 2. Select clock source by setting ASO as appropriate. 3. Write new values to TCNT0, OCR0 and TCCR0. 4. If switching to asynchronous operation, wait for TCNT0UB, OCR0UB and TCR0UB to be cleared. 5. Clear the Timer/Counter0 interrupt flags. 6. Enable interrupts if needed. * The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval 0 Hz 256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU main clock frequency. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. When writing to one of the registers TCNT0, OCR0 or TCCR0, the value is transferred to a temporary register and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register * 42 ATmega103(L) 0945G-09/01 ATmega103(L) have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to the destination register has taken place, an Asynchronous Status Register (ASSR) has been implemented. * When entering Power-save mode after having written to TCNT0, OCR0 or TCCR0, the user must wait until the written register has been updated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU will go to sleep before the changes have had any effect. This is extremely important if the Output Compare0 interrupt is used to wake up the device; Output Compare is disabled during write to OCR0 or TCNT0. If the write cycle is not finished (i.e., the user goes to sleep before the OCR0UB bit returns to zero), the device will never get a compare match and the MCU will not wake up. If Timer/Counter0 is used to wake up the device from Power-save mode, precautions must be taken if the user wants to reenter Power-save mode: The interrupt logic needs one TOSC1 cycle to get reset. If the time between wake-up and reentering Power-save mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR0, TCNT0 or OCR0. 2. Wait until the corresponding Update Busy flag in ASSR returns to zero. 3. Enter Power-save mode. * When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter0 is always running, except in Power-down mode. After a power-up reset or wake-up from power-down, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter0 after power-up or wake-up from Power-down. The content of all Timer/Counter0 registers must be considered lost after a wake-up from Power-down due to the unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the TOSC pin. Description of wake-up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake-up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. To execute the corresponding Timer/Counter0 interrupt routine, the global interrupt bit in SREG must have been set. Otherwise, the part will still wake up from Power-down, but continues to execute the Sleep command. The interrupt flags are updated three processor cycles after the processor clock has started. During these cycles, the processor executes instructions, but the interrupt condition is not readable and the interrupt routine has not started yet. During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock, and is not synchronized to the processor clock. After waking up from Power-save mode with the asynchronous timer enabled, there will be a short interval of which TCNT0 will read as the same value as before Powersave mode was entered. After an edge on the asynchronous clock, TCNT0 will read correctly. (The compare and overflow functions of the timer are not affected by this behavior.) Safe procedure to ensure correct value is read: * * * * 43 0945G-09/01 1. Write any value to either of the registers OCR0 or TCCR0 2. Wait for the corresponding Update Busy Flag to be cleared 3. Read TCNT0 Note that OCR0 and TCCR0 are never modified by hardware, and will always read correctly. 16-bit Timer/Counter1 Figure 33 shows the block diagram for Timer/Counter1. The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Register (TCCR1B). The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing functions with infrequent actions. The Timer/Counter1 supports two Output Compare functions using the Output Compare registers 1A and 1B (OCR1A and OCR1B) as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include optional clearing of the counter on compareA match, and actions on the Output Compare pins on both compare matches. 44 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 33. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ T/C1 COMPARE MATCHA IRQ T/C1 COMPARE T/C1 INPUT MATCHB IRQ CAPTURE IRQ 8-BIT DATA BUS OCIE1B OCIE1A OCF1B OCF1A TICIE1 OCIE2 TOIE2 TOIE1 OCIE0 TOIE0 OCF2 OCF0 TOV2 TIMER INT. MASK REGISTER (TIMSK) TIMER INT. FLAG REGISTER (TIFR) OCF1B OCF1A ICF1 TOV1 TOV1 ICF1 TOV0 T/C1 CONTROL REGISTER A (TCCR1A) PWM11 COM1A1 COM1B1 PWM10 COM1A0 COM1B0 T/C1 CONTROL REGISTER B (TCCR1B) CS12 ICNC1 CTC1 ICES1 CS10 CS11 15 87 T/C1 INPUT CAPTURE REGISTER (ICR1) 0 CONTROL LOGIC CK T1 CAPTURE TRIGGER 15 87 TIMER/COUNTER1 (TCNT1) 0 T/C CLEAR T/C CLOCK SOURCE UP/DOWN 15 8 7 0 15 8 7 0 16-BIT COMPARATOR 16-BIT COMPARATOR 15 8 7 0 15 8 7 0 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A TIMER/COUNTER1 OUTPUT COMPARE REGISTER B Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this mode the counter and the OCR1A/OCR1B registers serve as a dual glitch-free standalone PWM with centered pulses. Refer to page 50 for a detailed description of this function. The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture Register (ICR1), triggered by an external event on the Input Capture pin - PD4/(IC1). The actual capture event settings are defined by the Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be set to trigger the input capture. Refer to "Analog Comparator" on page 70 for details on this. The ICP pin logic is shown in Figure 34. Figure 34. ICP Pin Schematic Diagram 45 0945G-09/01 If the Noise Canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples, and all four must be equal to activate the capture flag. Timer/Counter1 Control Register A - TCCR1A Bit $2F ($4F) Read/Write Initial Value 7 COM1A1 6 COM1A0 5 COM1B1 4 COM1B0 3 - 2 - 1 PWM11 0 PWM10 TCCR1A R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 * Bits 7..6 - COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 15 * Bits 5..4 - COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. The control configuration is given in Table 15. Table 15. Compare1 Mode Select COM1X1 0 0 1 1 Note: COM1X0 0 1 0 1 Description Timer/Counter1 disconnected from output pin OC1X Toggle the OC1X output line. Clear the OC1X output line (to zero). Set the OC1X output line (to one). X = A or B. In PWM mode, these bits have a different function. Refer to Table 16 for a detailed description. * Bits 3..2 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. * Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 18 on page 50. This mode is described on page 50. Table 16. PWM Mode Select PWM11 0 0 1 1 PWM10 0 1 0 1 Description PWM operation of Timer/Counter1 is disabled. Timer/Counter1 is an 8-bit PWM. Timer/Counter1 is a 9-bit PWM. Timer/Counter1 is a 10-bit PWM. 46 ATmega103(L) 0945G-09/01 ATmega103(L) Timer/Counter1 Control Register B - TCCR1B Bit $2E ($4E) Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 - R 0 3 CTC1 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the input capture pin PD4(IC1) as specified. When the ICNC1 bit is set (one), four successive samples are measured on PD4(IC1), and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. * Bit 6 - ICES1: Input Capture1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the falling edge of the input capture pin - PD4(IC1). While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register on the rising edge of the input capture pin - PD4(IC1). * Bits 5, 4 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. * Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used and the compareA register is set to C, the timer will count as follows if CTC1 is set: ... | C-2 | C-1 | C | 0 | 1 | ... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ... In PWM mode, this bit has no effect. * Bits 2, 1, 0 - CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The lock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1. Table 17. Clock1 Prescale Select CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter1 is stopped. CK CK/8 CK/64 CK/256 CK/1024 External Pin T1, falling edge External Pin T1, rising edge 47 0945G-09/01 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK CPU clock. If the external pin modes are used for Timer/Counter1, transitions on PD6/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting. Timer/Counter1 - TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) 15 MSB 14 13 12 11 10 9 8 TCNT1H LSB TCNT1L 7 Read/Write Initial Value R/W R/W 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines). * TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit register write operation. When using Timer/Counter1 as an 8-bit timer, it is sufficient to write the low byte only. * TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data of TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. When using Timer/Counter1 as an 8-bit timer, it is sufficient to read the low byte only. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the clock cycle after it is preset with the written value. Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL Bit $2B $2A 15 MSB 14 13 12 11 10 9 8 OCR1AH LSB OCR1AL 7 Read/Write Initial Value R/W R/W 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 48 ATmega103(L) 0945G-09/01 ATmega103(L) Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL Bit $29 $28 15 MSB 14 13 12 11 10 9 8 OCR1BH LSB OCR1BL 7 Read/Write Initial Value R/W R/W 0 0 6 R/W R/W 0 0 5 R/W R/W 0 0 4 R/W R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 The Output Compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status registers. A compare match occurs only if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare registers (OCR1A and OCR1B) are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1 and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. Timer/Counter1 Input Capture Register - ICR1H and ICR1L Bit $27 ($37) $26 ($36) 15 MSB 14 13 12 11 10 9 8 ICR1H LSB ICR1L 7 Read/Write Initial Value R R 0 0 6 R R 0 0 5 R R 0 0 4 R R 0 0 3 R R 0 0 2 R R 0 0 1 R R 0 0 0 R R 0 0 The Input Capture Register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting (ICES1)) of the signal at the input capture pin - PD4(IC1) - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time, the input capture flag (ICF1) is set (one). Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. 49 0945G-09/01 The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A (OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit, free-running, glitch-free and phase-correct PWM with outputs on the PB5(OC1A) and PB6(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 16), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 10 least significant bits of OCR1A or OCR1B, the PB5(OC1A)/PB6(OC1B) pins are set or cleared according to the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register, TCCR1A. Refer to Table 19 for details. Table 18. Timer TOP Values and PWM Frequency PWM Resolution 8-bit 9-bit 10-bit Timer TOP value $00FF (255) $01FF (511) $03FF (1023) Frequency fTCK1/510 fTCK1/1022 fTCK1/2046 Table 19. Compare1 Mode Select in PWM Mode COM1X1 0 0 1 1 Note: COM1X0 0 1 0 1 X = A or B Effect on OCX1 Not connected Not connected Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example. 50 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 35. Effects on Unsynchronized OCR1 Latching Compare Value changes Counter Value Compare Value PWM Output OC1X Synchronized Compare Value changes OCR1X Latch Counter Value Compare Value PWM Output OC1X Unsynchronized Note: X = A or B OCR1X Latch Glitch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A/B. When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated to low or high on the next compare match according to the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20. Note: If the compare register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the upcounting and down-counting value is reached simultaneously. When the prescaler is in use (CS12..CS10 001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a one-period PWM pulse. Table 20. PWM Outputs OCR1X = $0000 or TOP COM1X1 1 1 1 1 Note: X = A or B COM1X0 0 0 1 1 OCR1X $0000 TOP $0000 TOP Output OC1X L H H L In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flags and interrupts. 51 0945G-09/01 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 21. See characterization data for typical values at other VCC levels. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. From the Watchdog reset, eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the ATmega103(L) resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 28. To prevent unintentional disabling of the Watchdog, a special turn-off procedure must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Figure 36. Watchdog Timer Oscillator 1 MHz at VCC = 5V 350 kHz at VCC = 3V Watchdog Timer Control Register - WDTCR Bit $21 ($41) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 WDTOE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. * Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared, Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. * Bit 3 - WDE: Watchdog Enable When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared (zero), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed: 52 ATmega103(L) 0945G-09/01 ATmega103(L) 1. In the same operation, write a logical "1" to WDTOE and WDE. A logical "1" must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical "0" to WDE. This disables the Watchdog. * Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 21. Table 21. Watchdog Timer Prescale Select WDP2 0 0 0 0 1 1 1 1 Note: WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Number of WDT Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Typical Time-out at VCC = 3.0V 47 ms 94 ms 0.19 s 0.38 s 0.75 s 1.5 s 3.0 s 6.0 s Typical Time-out at VCC = 5.0V 15 ms 30 ms 60 ms 0.12 s 0,24 s 0.49 s 0.97 s 1.9 s The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical Characteristics section. The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero. To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select. 53 0945G-09/01 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM control register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When it is read, the CPU is halted for four clock cycles. EEPROM Address Register - EEARH, EEARL Bit $1F ($3F) $1E ($3E) Read/Write Initial Value 15 - EEAR7 7 R R/W 0 0 14 - EEAR6 6 R R/W 0 0 13 - EEAR5 5 R R/W 0 0 12 - EEAR4 4 R R/W 0 0 11 EEAR11 EEAR3 3 R/W R/W 0 0 10 EEAR10 EEAR2 2 R/W R/W 0 0 9 EEAR9 EEAR1 1 R/W R/W 0 0 8 EEAR8 EEAR0 0 R/W R/W 0 0 EEARH EEARL The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address in the 4 KB EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4095. EEPROM Data Register - EEDR Bit $1D ($3D) Read/Write Initial Value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 EEDR * Bits 7..0 - EEDR7..0: EEPROM Data: For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. EEPROM Control Register - EECR Bit $1C ($3C) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W 0 0 EERE R/W 0 EECR * Bits 7..4 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always be read as zero. * Bit 3 - EERIE: EEPROM Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt constantly generates an interrupt request when EEWE is cleared (zero). 54 ATmega103(L) 0945G-09/01 ATmega103(L) * Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. * Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical "1" is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical "1" to the EEMWE bit in EECR (to be able to write an logical "1" to the EEMWE bit, the EEWE bit must be written to zero in the same cycle). 5. Within four clock cycles after setting EEMWE, write a logical "1" to EEWE. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR registers will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the four last steps to avoid these problems. When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined. 55 0945G-09/01 Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low. EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low VCC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to application note "AVR 180" for design considerations regarding power-on reset and low-voltage detection. 2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption. 56 ATmega103(L) 0945G-09/01 ATmega103(L) Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega103(L) and peripheral devices or between several AVR devices. The ATmega103(L) SPI features include the following: * * * * * * * Full-duplex, 3-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Four Programmable Bit Rates End-of-Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode (Slave Mode only) Figure 37. SPI Block Diagram The interconnection between master and slave CPUs with SPI is shown in Figure 38. The PB1 (SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI Data Register of the master CPU starts the SPI clock generator, and the data written shifts out of the PB2 (MOSI) pin and into the PB2 (MOSI) pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the end-of-transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB0(SS), is set low to select an individual slave SPI device. The two shift registers in the master and the slave can be considered as one distributed 16-bit circular shift register. This is shown in Figure 38. When data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged. 57 0945G-09/01 Figure 38. SPI Master-slave Interconnection MSB MASTER LSB MISO MISO MSB SLAVE LSB 8-BIT SHIFT REGISTER MOSI MOSI 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR SCK SS VCC SCK SS The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that characters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in. Otherwise, the first byte is lost. When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overridden according to the following table: Table 22. SPI Pin Overrides PIN MOSI MISO SCK SS Note: Direction, Master SPI User Defined Input User Defined User Defined Direction, Slave SPI Input User Defined Input Input See "Alternate Functions of Port B" on page 84 for a detailed description and how to define the direction of the user-defined SPI pins. SS Pin Functionality When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin that does not affect the SPI system. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starts to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmittal is used in master mode and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master mode. When the SPI is configured as a slave, the SS pin is always input. When SS is held low, the SPI is activated and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once 58 ATmega103(L) 0945G-09/01 ATmega103(L) the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. Data Modes There are four combinations of SCK phase and polarity with respect to serial data that are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 39 and Figure 40. Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0 SCK CYCLE # (FOR REFERENCE) SCK (CPOL=0) SCK (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) SAMPLE * Not defined but normally MSB of character just received. 1 2 3 4 5 6 7 8 MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB * Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK CYCLE # (FOR REFERENCE) SCK (CPOL=0) SCK (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) SAMPLE * Not defined but normally LSB of previously transmitted character. 1 2 3 4 5 6 7 8 MSB * MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB SPI Control Register - SPCR Bit $0D ($2D) Read/Write Initial Value 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR * Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. * Bit 6 - SPE: SPI Enable When the SPE bit is set (one), the SPI is enabled and SS, MOSI, MISO and SCK are connected to pins PB0, PB1, PB2 and PB3. * Bit 5 - DORD: Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. 59 0945G-09/01 * Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI master mode. * Bit 3 - CPOL: Clock Polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39 and Figure 40 for additional information. * Bit 2 - CPHA: Clock Phase Refer to Figure 39 or Figure 40 for the functionality of this bit. * Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the CPU Clock frequency (fcl) is shown in Table 23. Table 23. Relationship between SCK and the Oscillator Frequency SPR1 0 0 1 1 Note: SPR0 0 1 0 1 SCK Frequency fcl/4 fcl/16 fcl/64 fcl/128 Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. SPI Status Register - SPSR Bit $0E Read/Write Initial Value 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 SPSR * Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set (one), then accessing the SPI Data Register (SPDR). * Bit 6 - WCOL: Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register. * Bits 5..0 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. 60 ATmega103(L) 0945G-09/01 ATmega103(L) SPI Data Register - SPDR Bit $0F ($2F) Read/Write Initial Value 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X Undefined SPDR The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 61 0945G-09/01 UART The ATmega103(L) features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: * Baud Rate Generator that can Generate a large Number of Baud Rates (bps) * High Baud Rates at Low XTAL Frequencies * 8 or 9 Bits Data * Noise Filtering * Overrun Detection * Framing Error Detection * False Start Bit Detection * Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete A block schematic of the UART transmitter is shown in Figure 41. Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit Shift register when: * * A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately. A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. Data Transmission If the 10(11)-bit Transmit Shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to receive the next character. Writing to UDR clears UDRE. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit Shift register. 62 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 41. UART Transmitter DATA BUS XTAL BAUD RATE GENERATOR BAUD x 16 /16 UART I/O DATA REGISTER (UDR) STORE UDR SHIFT ENABLE PIN CONTROL LOGIC CONTROL LOGIC IDLE BAUD 10(11)-BIT TX SHIFT REGISTER 1 TXD UART CONTROL REGISTER (UCR) RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 DATA BUS TXC UDRE On the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin, followed by the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send when the stop bit is shifted out, the UDRE flag will remain set. In this case, after the stop bit has been present on TXD for one bit length, the TX Complete Flag (TXC) in USR is set. The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PE1 pin can be used for general I/O. When TXEN is set, the UART transmitter will be connected to PE1, which is forced to be an output pin regardless of the setting of the DDE1 bit in DDRE. RXC TXC UDRE FE OR UART STATUS REGISTER (USR) TXC IRQ UDRE IRQ 63 0945G-09/01 Data Reception Figure 42. UART Receiver DATA BUS XTAL BAUD RATE GENERATOR BAUD X 16 /16 BAUD UART I/O DATA REGISTER (UDR) STORE UDR PIN CONTROL LOGIC RXD DATA RECOVERY LOGIC 10(11)-BIT RX SHIFT REGISTER UART CONTROL REGISTER (UCR) RXCIE TXCIE UDRIE DATA BUS RXC IRQ The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical "0" will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at samples 8, 9, and 10. If two or more of these three samples are found to be logical "1"s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition. If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure 43. 64 ATmega103(L) 0945G-09/01 RXC RXC TXC UDRE FE DOR RXEN TXEN CHR9 RXB8 TXB8 UART STATUS REGISTER (USR) ATmega103(L) Figure 43. Sampling Received Data RXD START BIT RECEIVER SAMPLING D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical "0"s, the Framing Error (FE) flag in the UART Status Register (USR) is set when the received byte is transferred to UDR. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. FE is cleared when UDR is read. Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit Shift register when data is transferred to UDR. If, after having received a character, the UDR register has not been accessed since the last receive, the OverRun (OR) flag in USR is set. This means that the new data transferred to the shift register could not be transferred to UDR and is lost. The OR bit is buffered, and is available when the valid data byte in UDR has been read. The user should always check the OR after reading from the UDR register in order to detect any overruns if the baud rate is high or CPU load is high. When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This means that the PE0 pin can be used as a general I/O pin. When RXEN is set, the UART Receiver will be connected to PE0, which is forced to be an input pin regardless of the setting of the DDE0 bit in DDRE. When PE0 is forced to input by the UART, the PORTE0 bit can still be used to control the pull-up resistor on the pin. When the CHR9 bit in the UCR register is set, transmitted and received characters are 9 bits long plus start and stop bits. The 9th data bit to be transmitted is the TXB8 bit in UCR register. This bit must be set to the wanted value before a transmission is initated by writing to the UDR register. 65 0945G-09/01 UART Control UART I/O Data Register - UDR Bit $0C ($2C) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 UDR The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. UART Status Register - USR Bit $0B ($2B) Read/Write Initial Value 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 OR R 0 2 - R 0 1 - R 0 0 - R 0 USR The USR register is a read-only register providing information on the UART Status. * Bit 7 - RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. * Bit 6 - TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to the UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical "1" to the bit. * Bit 5 - UDRE: UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit Shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. * Bit 4 - FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. 66 ATmega103(L) 0945G-09/01 ATmega103(L) The FE bit is cleared when the stop bit of received data is one. * Bit 3 - OR: OverRun This bit is set if an overrun condition is detected, i.e., when a character already present in the UDR register is not read before the next character is transferred from the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. * Bits 2..0 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and will always read as zero. UART Control Register - UCR Bit $0A ($2A) Read/Write Initial Value 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 CHR9 R/W 0 1 RXB8 R 1 0 TXB8 W 0 UCR * Bit 7 - RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 6 - TXCIE: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty Interrupt routine to be executed, provided that global interrupts are enabled. * Bit 4 - RXEN: Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the RXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. * Bit 3 - TXEN: Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted. * Bit 2 - CHR9: 9-bit Characters When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit. * Bit 1 - RXB8: Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character. * Bit 0 - TXB8: Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted. 67 0945G-09/01 Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation: f CK BAUD = ------------------------------------16 ( UBRR + 1 ) * * * BAUD = baud rate fCK = CPU clock frequency UBRR = contents of the UART baud rate register, UBRR (0 - 255) For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in Table 24. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. UBRR values that yield an actual baud rate differing less than 2% from the target baud rate are in boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance. 68 ATmega103(L) 0945G-09/01 ATmega103(L) Table 24. UBRR Settings at Various CPU Frequencies Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 1 MHz %Error 1.8432 MHz %Error 2 MHz %Error 2.4576 MHz %Error UBRR= 25 0.2 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 63 0.0 UBRR= 12 0.2 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 31 0.0 UBRR= 6 7.5 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 15 0.0 UBRR= 3 7.8 UBRR= UBRR= 8 3.7 UBRR= 10 3.1 7 0.0 UBRR= 2 7.8 UBRR= 6 7.5 UBRR= 5 0.0 UBRR= 7 0.0 UBRR= 1 7.8 UBRR= 3 7.8 UBRR= 4 6.3 3 0.0 UBRR= UBRR= 1 22.9 UBRR= 2 7.8 UBRR= 2 0.0 UBRR= 3 0.0 UBRR= 0 7.8 UBRR= 1 7.8 UBRR= 2 12.5 1 0.0 UBRR= UBRR= 0 22.9 UBRR= 1 33.3 UBRR= 1 22.9 UBRR= 1 0.0 UBRR= 0 84.3 UBRR= 0 7.8 UBRR= 0 25.0 0 0.0 UBRR= 3.2768 MHz %Error 3.6864 MHz %Error 4 MHz %Error 4.608 MHz %Error UBRR= 84 0.4 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 42 0.8 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 20 1.6 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 UBRR= 16 2.1 UBRR= 13 1.6 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 10 3.1 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0 UBRR= 8 3.7 UBRR= 6 1.6 UBRR= 7 0.0 UBRR= 9 0.0 UBRR= 4 6.3 UBRR= 6 7.5 UBRR= 7 6.7 5 0.0 UBRR= UBRR= 3 12.5 UBRR= 3 7.8 UBRR= 3 0.0 UBRR= 4 0.0 UBRR= 2 12.5 UBRR= 2 7.8 UBRR= 3 6.7 2 0.0 UBRR= UBRR= 1 12.5 UBRR= 1 7.8 UBRR= 2 20.0 1 0.0 UBRR= 7.3728 MHz %Error 8 MHz %Error 9.216 MHz %Error 11.059 MHz %Error UBRR= 191 0.0 UBRR= 207 0.2 UBRR= 239 0.0 UBRR= 287 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 143 0.0 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 71 0.0 UBRR= 31 0.0 UBRR= 34 0.8 UBRR= 39 0.0 UBRR= 47 0.0 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 UBRR= 35 0.0 UBRR= 16 2.1 UBRR= 15 0.0 UBRR= 19 0.0 UBRR= 23 0.0 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0 UBRR= 17 0.0 UBRR= 8 3.7 UBRR= 7 0.0 UBRR= 9 0.0 UBRR= 11 0.0 UBRR= 6 7.5 UBRR= 7 6.7 UBRR= 5 0.0 UBRR= 8 0.0 UBRR= 3 7.8 UBRR= 3 0.0 UBRR= 4 0.0 UBRR= 5 0.0 UART Baud Rate Register - UBRR Bit $09 ($29) Read/Write Initial Value 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 UBRR The UBRR is an 8-bit read/write register that specifies the UART baud rate according to the description on the previous page. 69 0945G-09/01 Analog Comparator The analog comparator compares the input values on the positive input PE2 (AC+) and negative input PE3 (AC-). When the voltage on the positive input PE2 (AC+) is higher than the voltage on the negative input PE3 (AC-), the Analog Comparator Output (ACO) is set (one). The output of the comparator can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 44. Figure 44. Analog Comparator Block Diagram VCC ACD ACIE PE2 (AC+) + ANALOG COMPARATOR IRQ ACI ACIS1 ACIS0 ACIC INTERRUPT SELECT PE3 (AC-) ACO TO T/C1 CAPTURE TRIGGER MUX Analog Comparator Control and Status Register - ACSR Bit $08 ($28) Read/Write Initial Value 7 ACD R/W 0 6 - R 0 5 ACO R X 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is set (one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise, an interrupt can occur when the bit is changed. * Bit 6 - Res: Reserved Bit This bit is a reserved bit in the ATmega103(L) and will always read as zero. * Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical "1" to the flag. Observe, however, that if another bit in this register is modified 70 ATmega103(L) 0945G-09/01 ATmega103(L) using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is, in this case, directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one). * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 25. Table 25. ACIS1/ACIS0 Settings ACIS1 0 0 1 1 ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle Reserved Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise, an interrupt can occur when the bits are changed. Caution: Using the SBI or CBI instruction on other bits than ACI in this register will write a one back into ACI if it is read as set, thus clearing the flag. 71 0945G-09/01 Analog-to-Digital Converter Feature list: * * * * * * * * 10-bit Resolution 2 LSB Absolute Accuracy 0.5 LSB Integral Non-linearity 70 - 280 s Conversion Time Up to 14 kSPS 8 Multiplexed Input Channels Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The ATmega103(L) features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer, which allows each pin of Port F to be used as an input for the ADC. The ADC contains a Sample and Hold Amplifier, which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 45. The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must be connected to GND, and the voltage on AVCC must not differ more than 0.3V from VCC. See the section "ADC Noise Canceling Techniques" on page 77 on how to connect these pins. An external reference voltage must be applied to the AREF pin. This voltage must be in the range AGND - AVCC. Figure 45. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS External Reference Voltage ADIF ADIE 9 ADC DATA REGISTER (ADCH/ADCL) 0 ADC MULTIPLEXER SELECT (ADMUX) MUX2 MUX1 MUX0 ADC CTRL & STATUS REGISTER (ADCSR) ADEN ADSC ADIE ADIF ADPS2 ADPS1 ADPS0 10-BIT DAC 8CHANNEL MUX CONVERSION LOGIC Analog Inputs + SAMPLE & HOLD COMPARATOR 72 ATmega103(L) 0945G-09/01 ATmega103(L) Operation The ADC operates in Single Conversion mode, and each conversion will have to be initiated by the user. The ADC is enabled by writing a logical "1" to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started after enabling the ADC will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will be that this conversion takes 13 more ADC clock pulses than a normal conversion (see Figure 48). A conversion is started by writing a logical "1" to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the conversion is in progress and be set to zero by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. As the ADC generates a 10-bit result, two data registers, ADCH and ADCL, must be read to get the result when the conversion is complete. Special data protection logic is used to ensure that the contents of the data registers belong to the same result when they are read. This mechanism works as follows: When reading data, ADCL must be read first. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, none of the registers are updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled. The ADC has its own interrupt, ADIF, which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCL and ADCH, the interrupt will trigger even if the result is lost. Prescaling Figure 46. ADC Prescaler ADEN CK Reset 7-BIT ADC PRESCALER ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in poorer accuracy (see "ADC DC Characteristics" on page 78). The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler CK/128 CK/16 CK/32 CK/64 CK/2 CK/4 CK/8 73 0945G-09/01 keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following falling edge of the ADC clock cycle. The actual sample-and-hold takes place one ADC clock cycle after the start of the conversion. The result is ready and written to the ADC Result Register after 13 cycles. The ADC needs two more clock cycles before a new conversion can be started. If ADSC is set high in this period, the ADC will start the new conversion immediately. For a summary of conversion times, see Table 26. Figure 47. ADC Timing Diagram, First Conversion Cycle number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 ADC clock ADEN ADSC Hold strobe ADIF ADCH ADCL MSB of result LSB of result Dummy Conversion Actual Conversion Second Conversion Table 26. ADC Conversion Time Sample Cycle Number 14 1 Result Ready (Cycle Number) 26 13 Total Conversion Time (Cycles) 28 15 Total Conversion Time (s) 140 - 560 75 - 300 Condition 1st Conversion Single Conversion Figure 48. ADC Timing Diagram Cycle number ADC clock ADSC Hold strobe ADIF ADCH ADCL MSB of result LSB of result 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 One Conversion Next Conversion 74 ATmega103(L) 0945G-09/01 ATmega103(L) ADC Noise Canceler Function The ADC features a noise canceler that enables conversion during idle mode to reduce noise induced from the CPU core. To make use of this feature, the following procedure should be used: 1. Turn off the ADC by clearing ADEN. 2. Turn on the ADC and simultaneously start a conversion by setting ADEN and ADSC. This starts a dummy conversion that will be followed by a valid conversion. 3. Within 14 ADC clock cycles, enter idle mode. 4. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the MCU and execute the ADC conversion complete interrupt routine. ADC Multiplexer Select Register - ADMUX Bit $07 ($27) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATmega103(L) and always read as zero. * Bits 2..0 - MUX2..MUX0: Analog Channel Select Bits 2 - 0 The value of these three bits selects which analog input 7 - 0 is connected to the ADC. ADC Control and Status Register - ADCSR Bit $06 ($26) Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 - R 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSR * Bit 7 - ADEN: ADC Enable Writing a logical "1" to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion A logical "1" must be written to this bit to start each conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated conversion. This dummy conversion performs initialization of the ADC. ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written to the ADC Data registers. This allows a new conversion to be initiated before the current conversion is complete. The new conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a zero to this bit has no effect. * Bit 5 - Res: Reserved Bit This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical "0" must be written to this bit. 75 0945G-09/01 * Bit 4 - ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion is complete and the result is written to the ADC Data registers are updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical "1" to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete interrupt is activated. * Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 27. ADC Prescaler Selections ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor Invalid 2 4 8 16 32 64 128 ADC Data Register - ADCL and ADCH Bit $05 ($25) $04 ($24) Read/Write Initial Value 15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL When an ADC conversion is complete, the result is found in these two registers. It is essential that both registers are read and that ADCL is read before ADCH. 76 ATmega103(L) 0945G-09/01 ATmega103(L) ADC Noise Canceling Techniques Digital circuitry inside and outside the ATmega103(L) generates EMI, which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATmega103(L) and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. 2. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 3. The AVCC pin on the ATmega103(L) should have its own decoupling capacitor as shown in Figure 49. 4. Use the ADC Noise Canceler function to reduce induced noise from the CPU. 5. If some Port F pins are used as digital inputs, it is essential that these do not switch while a conversion is in progress. Figure 49. ADC Power Connections (AD0) PA0 VCC GND (ADC7) PF7 (ADC6) PF6 (ADC5) PF5 (ADC4) PF4 (ADC3) PF3 (ADC2) PF2 (ADC1) PF1 (ADC0) PF0 AREF AGND AVCC 10nF Analog Ground Plane 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 PEN ATmega103(L) 77 0945G-09/01 ADC DC Characteristics TA = -40C to 85C Symbol Parameter Resolution Absolute accuracy Absolute accuracy Absolute accuracy Integral Non-linearity Differential Non-linearity Zero Error (Offset) Conversion Time Clock Frequency AVCC Analog Supply Voltage Reference Voltage Reference Input Resistance Analog Input Resistance 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 6.0V. 70 50 VREF = 4V, VCC = 4V ADC clock = 200 kHz VREF = 4V, VCC = 4V ADC clock = 1 MHz VREF = 4V, VCC = 4V ADC clock = 2 MHz VREF > 2V VREF > 2V Condition Min Typ 10 1 4 16 0.5 0.5 1 280 200 2 Max Units Bits LSB LSB LSB LSB LSB LSB s kHz VCC - 0.3(1) VCC + 0.3(2) V VREF 2 AVCC V RREF 6 10 13 k RAIN Notes: 100 M 78 ATmega103(L) 0945G-09/01 ATmega103(L) Interface to External SRAM The interface to the SRAM consists of: Port A: multiplexed low-order address bus and data bus Port C: high-order address bus The ALE pin: address latch enable The RD and WR pin: read and write strobes The external data SRAM is enabled by setting the external SRAM enable bit (SRE) of the MCU Control Register (MCUCR) and will override the setting of the data direction register (DDRA). When the SRE bit is cleared (zero), the external data SRAM is disabled and the normal pin and data direction settings are used. When SRE is cleared (zero), the address space above the internal SRAM boundary is not mapped into the internal SRAM as AVR parts do not have an interface to the external SRAM. When ALE goes from high to low, there is a valid address on Port A. ALE is low during a data transfer. RD and WR are active when accessing the external SRAM only. When the external SRAM is enabled, the ALE signal may have short pulses when accessing the internal RAM, but the ALE signal is stable when accessing the external SRAM. Figure 50 shows how to connect an external SRAM to the AVR using eight latches that are transparent when G is high. By default, the external SRAM access is a three-cycle scheme as depicted in Figure 51. When one extra wait state is needed in the access cycle, set the SRW bit (one) in the MCUCR register. The resulting access scheme is shown in Figure 52. In both cases, note that Port A is data bus in one cycle only. As soon as the data access finishes, Port A becomes a low-order address bus again. Note: If a read is followed by a write, or vice versa, there is no extra insertion of wait states in between. The user may insert a NOP between consecutive read and write operations to the external RAM, because such short time for releasing the bus is difficult to obtain without making bus contention. For details on the timing for the SRAM interface, please refer to Figure 79, Table 45, Table 46, Table 47, and Table 48 in the section "DC Characteristics" on page 113 and refer to "Architectural Overview" on page 8 for a description of the memory map, including address space for SRAM. Figure 50. External SRAM Connected to the AVR D[7:0] Port A D Q A[7:0] ALE G SRAM AVR Port C RD WR A[15:8] RD WR 79 0945G-09/01 Figure 51. External SRAM Access Cycle without Wait States T1 T2 T3 System Clock O ALE Address [15..8] Data / Address [7..0] WR Data / Address [7..0] RD Prev. Address Address Data Address Prev. Address Prev. Address Address Address Data Address Figure 52. External SRAM Access Cycle with Wait State T1 T2 T3 T4 System Clock O ALE Address [15..8] Data / Address [7..0] WR Data / Address [7..0] RD Prev. Address Address Data Addr . Prev. Address Prev. Address Address Address Data Addr . 80 ATmega103(L) 0945G-09/01 Read Write Read Write ATmega103(L) I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port A is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port A, one each for the Data Register - PORTA, $1B($3B), Data Direction Register - DDRA, $1A($3A) and the Port A Input Pins - PINA, $19($39). The Port A Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port A output buffers can sink 20 mA and thus drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins have alternate functions related to the optional external data SRAM. Port A can be configured to be the multiplexed low-order address/data bus during accesses to the byte. When Port A is set to the alternate function by the SRE (External SRAM Enable) bit in the MCUCR (MCU Control Register), the alternate settings override the data direction register. Port A Data Register - PORTA Bit $1B ($3B) Read/Write Initial Value 7 PORTA7 Port A 6 PORTA6 5 PORTA5 4 PORTA4 3 PORTA3 2 PORTA2 1 PORTA1 0 PORTA0 PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port A Data Direction Register - DDRA Bit $1A ($3A) Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA Port A Input Pins Address - PINA Bit $19 ($39) Read/Write Initial Value 7 PINA7 R N/A 6 PINA6 R N/A 5 PINA5 R N/A 4 PINA4 R N/A 3 PINA3 R N/A 2 PINA2 R N/A 1 PINA1 R N/A 0 PINA0 R N/A PINA The Port A Input Pins address (PINA) is not a register; this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read and when reading PINA, the logical values present on the pins are read. Port A as General Digital I/O All eight pins in Port A have equal functionality when used as digital I/O pins. PAn, general I/O pin: The DDAn bit in the DDRA register selects the direction of this pin. If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, PORTAn has 81 0945G-09/01 to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 28. DDAn Effects on Port A Pins DDAn 0 0 1 1 Note: PORTAn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PAn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output n: 7,6...0, pin number Port A Schematics Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7) RD MOS PULLUP RESET R Q D DDAn C RESET R Q D PORTAn C RL PAn WP An Dn W R SRE RP WP: WD: RL: RP: RD: SRE: A: D: W: R: n: WRITE PORTA WRITE DDRA READ PORTA LATCH READ PORTA PIN READ DDRA EXT. SRAM ENABLE ADDRESS DATA WRITE READ 0-7 SRE R W An Dn Port B Port B is an 8-bit bi-directional I/O port with internal pull-ups. Three I/O memory address locations are allocated for Port B, one each for the Data Register - PORTB, $18($38), Data Direction Register - DDRB, $17($37) and the Port B Input Pins - PINB, $16($36). The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as 82 ATmega103(L) 0945G-09/01 DATA BUS WD ATmega103(L) inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins with alternate functions are shown in Table 29. Table 29. Port B Pin Alternate Functions Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Alternate Functions SS (SPI Slave Select input) SCK (SPI Bus Serial Clock) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) OC0/PWM0 (Output Compare and PWM Output for Timer/Counter0) OC1A/PWM1A (Output Compare and PWM Output A for Timer/Counter1) OC1B/PWM1B (Output Compare and PWM Output B for Timer/Counter1) OC2/PWM2 (Output Compare and PWM Output for Timer/Counter2) When the pins are used for the alternate function, the DDRB and PORTB registers have to be set according to the alternate function description. Port B Data Register - PORTB Bit $18 ($38) Read/Write Initial Value 7 PORTB7 6 PORTB6 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port B Data Direction Register - DDRB Bit $17 ($37) Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB Port B Input Pins Address - PINB Bit $16 ($36) Read/Write Initial Value 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read and when reading PINB, the logical values present on the pins are read. Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running. 83 0945G-09/01 Table 30. DDBn Effects on Port B Pins DDBn 0 0 1 1 Note: PORTBn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PBn will source current if ext. pulled low Push-pull Zero Output Push-pull One Output n: 7,6...0, pin number Alternate Functions of Port B The alternate pin configuration is as follows: * OC2/PWM2, Bit 7 OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when Timer/Counter2 is in PWM Mode. The pin has to be configured as an output to serve this function. * OC1B/PWM1B, Bit 6 OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when Timer/Counter1 is in PWM Mode. The pin has to be configured as an output to serve this function. * OC1A/PWM1A, Bit 5 OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when Timer/Counter1 is in PWM Mode. The pin has to be configured as an output to serve this function. * OC0/PWM0, Bit 4 OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when Timer/Counter0 is in PWM Mode. The pin has to be configured as an output to serve this function. * MISO - Port B, Bit 3 MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. See the description of the SPI port for further details. * MOSI - Port B, Bit 2 MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. See the description of the SPI port for further details. * SCK - Port B, Bit 1 SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. See the description of the SPI port for further details. 84 ATmega103(L) 0945G-09/01 ATmega103(L) * SS - Port B, Bit 0 SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. See the description of the SPI port for further details. Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 54. Port B Schematic Diagram (Pin PB0) 85 0945G-09/01 Figure 55. Port B Schematic Diagram (Pin PB1) Figure 56. Port B Schematic Diagram (Pin PB2) 86 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 57. Port B Schematic Diagram (Pin PB3) Figure 58. Port B Schematic Diagram (Pin PB4) RD MOS PULLUP RESET R Q D DDB4 C RESET R Q D PORTB4 C RL PB4 WP RP WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB COM01 COM01 OUTPUT MODE SELECT COMP. MATCH 0 DATA BUS WD 87 0945G-09/01 Figure 59. Port B Schematic Diagram (Pins PB5 and PB6) RD MOS PULLUP RESET R Q D DDBn C RESET R Q D PORTBn C RL PBn WP RP WP: WD: RL: RP: RD: n: X: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB 5, 6 A, B COM1X0 COM1X1 OUTPUT MODE SELECT COMP. MATCH 1X Figure 60. Port B Schematic Diagram (Pin PB7) RD MOS PULLUP RESET R Q D DDB7 C RESET R Q D PORTB7 C RL PB7 WP RP WP: WD: RL: RP: RD: WRITE PORTB WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB COM20 COM21 OUTPUT MODE SELECT COMP. MATCH 2 88 ATmega103(L) 0945G-09/01 DATA BUS WD DATA BUS WD ATmega103(L) Port C Port C is an 8-bit output port. The Port C pins have alternate functions related to the optional external data SRAM. When using the device with external SRAM, Port C outputs the high-order address byte during accesses to external data memory. When a reset condition becomes active, the port pins are not tri-stated, but the pins will assume their initial value after two stable clock cycles. The Port C Data Register - PORTC Bit $15 ($35) Read/Write Initial Value 7 PORTC7 6 PORTC6 5 PORTC5 4 PORTC4 3 PORTC3 2 PORTC2 1 PORTC1 0 PORTC0 PORTC R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port C Schematics Figure 61. Port C Schematic Diagram (Pins PC0 - PC7) RESET R Q D PORTCn C RL PCn WP WP: RL: A: SRE: n: WRITE PORTC READ PORTC LATCH SRAM ADDRESS EXTERNAL SRAM ENABLE 0-7 SRE An Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port D Input Pins - PIND, $10($30). The Port D Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Some Port D pins have alternate functions as shown in Table 31. Table 31. Port D Pin Alternate Functions Port Pin PD0 PD1 PD2 PD3 PD4 PD6 PD7 Alternate Function INT0 (External Interrupt0 Input) INT1 (External Interrupt1 Input) INT2 (External Interrupt2 Input) INT3 (External Interrupt3 Input) IC1 (Timer/Counter1 Input Capture Trigger) T1 (Timer/Counter1 Clock Input) T2 (Timer/Counter2 Clock Input) DATA BUS 89 0945G-09/01 When the pins are used for the alternate function, the DDRD and PORTD registers have to be set according to the alternate function description. Port D Data Register - PORTD Bit $12 Read/Write Initial Value 7 PORTD7 6 PORTD6 5 PORTD5 4 PORTD4 3 PORTD3 2 PORTD2 1 PORTD1 0 PORTD0 PORTD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port D Data Direction Register - DDRD Bit $11 Read/Write Initial Value 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD Port D Input Pins Address - PIND Bit $10 Read/Write Initial Value 7 PIND7 R N/A 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are tristated when a reset condition becomes active, even if the clock is not running. Table 32. DDDn Bits on Port D Pins DDDn 0 0 1 1 Note: PORTDn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PDn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output n: 7,6...0, pin number Alternate Functions of Port D The alternate pin functions of Port D are: * INT0..INT3 - Port D, Bits 0..3 External Interrupt sources 0 - 3. The PD0 - PD3 pins can serve as external active low interrupt sources to the MCU. The internal pull-up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the sources. * IC1 - Port D, Bit 4 IC1, Input Capture pin for Timer/Counter1. When a positive or negative (selectable) edge is applied to this pin, the contents of Timer/Counter1 is transferred to the Timer/Counter1 Input Capture Register. The pin has to be configured as an input to 90 ATmega103(L) 0945G-09/01 ATmega103(L) serve this function. See the Timer/Counter1 description on how to operate this function. The internal pull-up MOS resistor can be activated as described above. * T1 - Port D, Bit 6 T1, Timer/Counter1 counter source. See the timer description for further details. * T2 - Port D, Bit 7 T2, Timer/Counter2 counter source. See the timer description for further details. Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3) RD MOS PULLUP RESET R Q D DDDn C RESET R Q D PORTDn C RL PDn WP RP WP: WD: RL: RP: RD: n: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 0, 1, 2, 3 INTn DATA BUS WD 91 0945G-09/01 Figure 63. Port D Schematic Diagram (Pin PD4) RD MOS PULLUP RESET R Q D DDD4 C RESET R Q D PORTD4 C RL PD4 WP RP WP: WD: RL: RP: RD: ACIC: ACO: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD COMPARATOR IC ENABLE COMPARATOR OUTPUT 0 NOISE CANCELER 1 ICNC1 ICES1 ACIC ACO EDGE SELECT ICF1 Figure 64. Port D Schematic Diagram (Pin PD5) RD MOS PULLUP RESET R Q D DDD5 C RESET R Q D PORTD5 C RL PD5 WP RP WP: WD: RL: RP: RD: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 92 ATmega103(L) 0945G-09/01 DATA BUS WD DATA BUS WD ATmega103(L) Figure 65. Port D Schematic Diagram (Pins PD6 and PD7) RD MOS PULLUP RESET R Q D DDDn C RESET R Q D PORTDn C RL PDn WP RP WP: WD: RL: RP: RD: n: m: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 6, 7 1, 2 SENSE CONTROL TIMERm CLOCK SOURCE MUX CSm2 CSm1 CSm0 Port E Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port E, one each for the Data Register - PORTE, $03($23), Data Direction Register - DDRE, $02($22) and the Port E Input Pins - PINE, $01($21). The Port E Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. All Port E pins have alternate functions as shown in Table 33. Table 33. Port E Pin Alternate Functions Port Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Alternate Function PDI/RXD (Programming Data Input or UART Receive Pin) PDO/TXD (Programming Data Output or UART Transmit Pin) AC+ (Analog Comparator Positive Input) AC- (Analog Comparator Negative Input) INT4 (External Interrupt4 Input) INT5 (External Interrupt5 Input) INT6 (External Interrupt6 Input) INT7 (External Interrupt7 Input) When the pins are used for the alternate function, the DDRE and PORTE registers have to be set according to the alternate function description. DATA BUS WD 93 0945G-09/01 Port E Data Register - PORTE Bit $03 ($23) Read/Write Initial Value 7 PORTE7 6 PORTE6 5 PORTE5 4 PORTE4 3 PORTE3 2 PORTE2 1 PORTE1 0 PORTE0 PORTE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port E Data Direction Register - DDRE Bit $02 ($22) Read/Write Initial Value 7 DDE7 R/W 0 6 DDE6 R/W 0 5 DDE5 R/W 0 4 DDE4 R/W 0 3 DDE3 R/W 0 2 DDE2 R/W 0 1 DDE1 R/W 0 0 DDE0 R/W 0 DDRE Port E Input Pins Address - PINE Bit $01 ($21) Read/Write Initial Value 7 PINE7 R N/A 6 PINE6 R N/A 5 PINE5 R N/A 4 PINE4 R N/A 3 PINE3 R N/A 2 PINE2 R N/A 1 PINE1 R N/A 0 PINE0 R N/A PINE The Port E Input Pins address (PINE) is not a register; this address enables access to the physical value on each Port E pin. When reading PORTE, the Port E Data Latch is read and when reading PINE, the logical values present on the pins are read. Port E as General Digital I/O PEn, general I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If DDEn is set (one), PEn is configured as an output pin. If DDEn is cleared (zero), PEn is configured as an input pin. If PEn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PEn has to be cleared (zero) or the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes active, even if the clock is not running. Table 34. DDEn Bits on Port E Pins DDEn 0 0 1 1 Note: PORTEn 0 1 0 1 I/O Input Input Output Output Pull-up No Yes No No Comment Tri-state (high-Z) PDn will source current if ext. pulled low. Push-pull Zero Output Push-pull One Output n: 7,6...0, pin number Alternate Functions of Port E The alternate pin functions of Port E are: * PDI/RXD - Port E, Bit 0 PDI, Serial Programming Data Input. During Serial Program downloading, this pin is used as data input line for the ATmega103(L). RXD, UART Receive Pin. Receive Data (Data input pin for the UART). When the UART receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical "1" in PORTD0 will turn on the internal pull-up. * PDO/TXD - Port E, Bit 1 PDO, Serial Programming Data Output. During Serial Program downloading, this pin is used as data output line for the ATmega103(L). TXD, UART Transmit Pin. 94 ATmega103(L) 0945G-09/01 ATmega103(L) * AC+ - Port E, Bit 2 AC+, Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. * AC- - Port E, Bit 3 AC-, Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. * INT4..INT7 - Port E, Bits 4 - 7 INT4..INT7, External Interrupt sources 4 - 7: The PE4 - PE7 pins can serve as external interrupt sources to the MCU. Interrupts can be triggered by low level or positive or negative edge on these pins. The internal pull-up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the sources. Port E Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 66. Port E Schematic Diagram (Pin PE0) 95 0945G-09/01 Figure 67. Port E Schematic Diagram (Pin PE1) Figure 68. Port E Schematic Diagram (Pin PE2) RD MOS PULLUP RESET Q D DDE2 C RESET PE2 Q D PORTE2 C RL WP RP TO COMPARATOR WP: WD: RL: RP: RD: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE AC+ 96 ATmega103(L) 0945G-09/01 DATA BUS WD ATmega103(L) Figure 69. Port E Schematic Diagram (Pin PE3) RD MOS PULLUP RESET Q D DDE3 C RESET PE3 Q D PORTE3 C RL WP RP TO COMPARATOR WP: WD: RL: RP: RD: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE AC- Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7) RD MOS PULLUP RESET R Q D DDEn C RESET R Q D PORTEn C RL PEn WP RP WP: WD: RL: RP: RD: n: WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE 4, 5, 6, 7 SENSE CONTROL INTn ISCn1 ISCn0 DATA BUS WD DATA BUS WD 97 0945G-09/01 Port F Port F is an 8-bit input port. One I/O memory location is allocated for Port F, the Port F Input Pins - PINF, $00 ($20). All Port F pins are connected to the analog multiplexer, which further is connected to the A/D converter. The digital input function of Port F can be used together with the A/D converter, allowing the user to use some pins of Port F and digital inputs and other as analog inputs, at the same time. Port F Input Pins Address - PINF Bit $00 ($20) Read/Write Initial Value 7 PINF7 R N/A 6 PINF6 R N/A 5 PINF5 R N/A 4 PINF4 R N/A 3 PINF3 R N/A 2 PINF2 R N/A 1 PINF1 R N/A 0 PINF0 R N/A PINF The Port F Input Pins address (PINF) is not a register; this address enables access to the physical value on each Port F pin. Figure 71. Port F Schematic Diagram (Pins PF7 - PF0) RP PFn TO ADC MUX RP: n: READ PORTF PIN 0-7 AINn 98 ATmega103(L) 0945G-09/01 DATA BUS ATmega103(L) Memory Programming Program and Data Memory Lock Bits The ATmega103(L) MCU provides two Lock bits that can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 35. The Lock bits can only be erased to "1" with the Chip Erase command. Table 35. Lock Bit Protection Modes Memory Lock Bits Mode 1 2 3 Note: LB1 1 0 0 LB2 1 1 0 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled.(1) Same as mode 2, and verify is also disabled. Protection Type 1. In Parallel mode, programming of the Fuse bits are also disabled. Program the Fuse bits before programming the Lock bits. Fuse Bits The ATmega103(L) has four Fuse bits, SPIEN, SUT1..0 and EESAVE. * When the SPIEN Fuse is programmed ("0"), Serial Program and Data Downloading is enabled. Default value is programmed ("0"). The SPIEN Fuse is not accessible in serial programming mode. When EESAVE is programmed, the EEPROM memory is preserved through the Chip Erase cycle. Default value is unprogrammed ("1"). The EESAVE Fuse bit cannot be programmed if any of the Lock bits are programmed. SUT1..0 Fuses: Determine the MCU start-up time. See Table 5 on page 26 for further details. Default value is unprogrammed ("11"), which gives a nominal start-up time of 16 ms. * * The status of the Fuse bits is not affected by Chip Erase. Signature Bytes All Atmel microcontrollers have a 3-byte signature code that identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space. For the ATmega103 they are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $97 (indicates 128K bytes Flash memory) 3. $002: $01 (indicates ATmega103 when signature byte $001 is $97) Programming the Flash and EEPROM Atmel's ATmega103(L) offers 128K bytes of In-System reprogrammable Flash memory and 4K bytes of EEPROM data memory. The ATmega103(L) is shipped with the On-chip Flash program and EEPROM data memory arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a parallel programming mode and a serial programming mode. The +12V supplied to the RESET pin in parallel programming mode is used for programming enable only, and no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download program and data into the ATmega103(L) inside the user's system. 99 0945G-09/01 The Flash program memory array on the ATmega103(L) is organized as 512 pages of 256 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously in either programming mode. The EEPROM data memory array on the ATmega103(L) is programmed byte-by-byte in either programming mode. An auto-erase cycle is provided within the self-timed EEPROM write instruction in the serial programming mode. During programming, the supply voltage must be in accordance with Table 36. Table 36. Supply Voltage during Programming Part ATmega103 ATmega103L Serial Programming 4.0 - 5.0V 3.2 - 3.6V Parallel Programming 4.0 - 5.0V 3.2 - 5.0V Parallel Programming This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the ATmega103(L). Pulses are assumed to be at least 500 ns unless otherwise noted. In this section, some pins of the ATmega103(L) are referenced by signal names describing their function during parallel programming (see Figure 72 and Table 37). Pins not described in Table 37 are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 38. When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions, as shown in Table 39. Figure 72. Parallel Programming ATmega103(L) VCC RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12V PD1 PD2 PD3 PD4 PD5 PD6 PA0 RESET PD7 XTAL1 GND VCC PB7 - PB0 DATA Signal Names 100 ATmega103(L) 0945G-09/01 ATmega103(L) . Table 37. Pin Name Mapping Signal Name in Programming Mode RDY/BSY OE WR BS1 XA0 XA1 BS2 PAGEL DATA Pin Name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7-0 I/O O I I I I I I I I/O Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (active low) Write Pulse (active low) Byte Select 1 ("0" selects low byte, "1" selects high byte) XTAL Action Bit 0 XTAL Action Bit 1 Byte Select 2 (always low) Program Memory Page Load Bi-directional Data Bus (output when OE is low) Table 38. XA1 and XA0 Coding XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1) Load Data (High or low data byte for Flash determined by BS1) Load Command No Action, Idle Table 39. Command Byte Bit Coding Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse Bits Write Lock Bits Write Flash Write EEPROM Read Signature Bytes Read Lock and Fuse Bits Read Flash Read EEPROM 101 0945G-09/01 Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply supply voltage according to Table 36, between VCC and GND. 2. Set RESET and BS1 pins to "0" and wait at least 100 ns. 3. Apply 11.5 - 12.5V to RESET. Any activity on BS1 within 100 ns after +12V has been applied to RESET will cause the device to fail entering programming mode. Chip Erase The Chip Erase will erase the Flash and EEPROM memories, and Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A chip erase must be performed before the Flash or EEPROM is reprogrammed. Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 40 for tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY pin. Table 40. Minimum WR Pulse Width for Chip Erase Symbol tWLWH_CE 3.2V 56 ms 3.6V 43 ms 4.0V 35 ms 5.0V 22 ms Programming the Flash The Flash is organized as 512 pages of 256 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A: Load Command "Write Flash". 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address Low Byte. 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address low byte ($00 - $FF) 4. Give XTAL1 a positive pulse. This loads the address low byte. C: Load Data Low Byte. 1. Set BS1 to "0". This selects low data. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data low byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data byte. D: Latch Data Low Byte. 1. Give PAGEL a positive pulse. This latches the data low byte. (See Figure 73 for signal waveforms.) 102 ATmega103(L) 0945G-09/01 ATmega103(L) E: Load Data High Byte. 1. Set BS1 to "1". This selects high data. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data high byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the data high byte. F: Latch Data High Byte. 1. Give PAGEL a positive pulse. This latches the data high byte. G: Repeat B through F 128 times to fill the page buffer. H: Load Address High Byte. 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address high byte ($00 - $FF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I: Program Page. 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high. (See Figure 74 for signal waveforms.) J: End Page Programming. 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA = "0000 0000". This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command and the internal write signals are reset. K: Repeat A through J 512 times or until all data has been programmed. Figure 73. Programming the Flash Waveforms DATA $10 ADDR. LOW ADDR. HIGH DATA LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY RESET +12V OE BS2 PAGEL 103 0945G-09/01 Figure 74. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET OE PAGEL BS2 +12V Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 102 for details on command, address and data loading): 1. A: Load Command "0001 0001". 2. H: Load Address High Byte ($00 - $0F). 3. B: Load Address Low Byte ($00 - $FF). 4. E: Load Data Low Byte ($00 - $FF). L: Write Data Low Byte. 1. Set BS to "0". This selects low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 75 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: * * * The command needs only be loaded once when writing or reading multiple memory locations. Address high byte needs only be loaded before programming a new 256-word page in the EEPROM. Skip writing the data value $FF that is the contents of the entire EEPROM after a chip erase. These considerations also apply to Flash, EEPROM and signature bytes reading. 104 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 75. Programming the EEPROM Waveforms DATA $11 ADDR. HIGH ADDR. LOW DATA LOW XA1 XA2 BS1 XTAL1 WR RDY/BSY RESET +12V OE BS2 PAGEL Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 102 for details on command and address loading): 1. A: Load Command "0000 0010". 2. H: Load Address High Byte ($00 - $FF). 3. B: Load Address Low Byte ($00 - $FF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1". Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 102 for details on command and address loading): 1. A: Load Command "0000 0011". 2. H: Load Address High Byte ($00 - $0F). 3. B: Load Address ($00 - $FF). 4. Set OE to "0", and BS1 to "0". The EEPROM data byte can now be read at DATA. 5. Set OE to "1". Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to "Programming the Flash" on page 102 for details on command and data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Bit 5 = SPIEN Fuse bit Bit 3 = EESAVE Fuse bit Bit 2 = always "1" 105 0945G-09/01 Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Bit 7, 6, 4, 2 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. Give WR a tWLWH_PFB wide negative pulse to execute the programming. tWLWH_PFB is found in Table 41. Programming the Fuse bits does not generate any activity on the RDY/BSY pin. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 102 for details on command and data loading): 1. A: Load Command "0010 0000". 2. D: Load Data Low Byte. Bit n = "0" programs the Lock bit. Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 Bit 7 - 3, 0 = "1". These bits are reserved and should be left unprogrammed ("1"). 3. L: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 102 for details on command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", and BS to "0". The status of the Fuse bits can now be read at DATA ("0" means programmed). Bit 5 = SPIEN Fuse bit Bit 3 = EESAVE Fuse bit Bit 1 = SUT1 Fuse bit Bit 0 = SUT0 Fuse bit Set OE to "0", and BS to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 3. Set OE to "1". Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to "Programming the Flash" on page 102 for details on command and address loading): 1. A: Load Command "0000 1000". 2. C: Load Address Low Byte ($00 - $02). Set OE to "0", and BS to "0". The selected signature byte can now be read at DATA. 3. Set OE to "1". 106 ATmega103(L) 0945G-09/01 ATmega103(L) Parallel Programming Characteristics Figure 76. Parallel Programming Timing tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1) tBVXH PAGEL WR RDY/BSY tWLRH tOLDV tPHPL tPLWL tPLBX t BVWL tWLWH tWHRL tRHBX tXHXL tXLDX DATA Table 41. Parallel Programming Characteristics TA = 25C 10%, VCC = 5V 10% Symbol VPP IPP tDVXH tXHXL tXLDX tXLWL tBVXH tPHPL tPLBX tPLWL tBVWL tRHBX tWLWH tWHRL tWLRH tXLOL tOLDV tOHDZ tWLWH_CE tWLWH_PFB Notes: Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low BS1 Valid before XTAL1 High PAGEL Pulse Width High BS1 Hold after PAGEL Low PAGEL Low to WR Low BS1 Valid to WR Low BS1 Hold after RDY/BSY High WR Pulse Width Low (1) Min 11.5 Typ Max 12.5 250 Units V A ns ns ns ns ns ns ns ns ns ns ns 67 67 67 67 67 67 67 67 67 67 67 20 0.5 67 20 20 5 1.0 10 1.5 15 1.8 0.7 0.9 WR High to RDY/BSY Low(2) WR Low to RDY/BSY High XTAL1 Low to OE Low OE Low to DATA Valid OE High to DATA Tri-stated WR Pulse Width Low for Chip Erase WR Pulse Width Low for Progr. the Fuse Bits (2) ns ms ns ns ns ms ms 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for programming the fuse bits. 2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen. 107 0945G-09/01 Read OE tXLOL tOHDZ Write Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial interface while RESET is pulled to GND, or when PEN is low during Power-on Reset. The serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase instructions can be executed. For the EEPROM, an auto-erase cycle is provided within the self-timed Write instruction and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM arrays into $FF. The program and EEPROM memory arrays have separate address spaces: $0000 to $FFFF for program memory and $0000 to $0FFF for EEPROM memory. Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 XTAL1 clock cycles High: > 2 XTAL1 clock cycles Figure 77. Serial Programming ATmega103(L) VCC VCC INSTR. IN DATA OUT CLOCK IN PE0 (PD1/RXD) PE1 (PD0/TXD) PB1 (SCK) XTAL1 RESET GND Note: Instruction in and data out is not using the SPI pins as on other AVR devices. SCK uses the SPI pin as usual. Serial Programming Algorithm When writing serial data to the ATmega103(L), data is sampled by the ATmega 103/103L on the rising edge of SCK. When reading data from the ATmega103(L), data is clocked on the falling edge of SCK. See Figure 78 for an explanation. To program and verify the ATmega103(L) in the serial programming mode, the following sequence is recommended (See 4-byte instruction formats in Table 44.): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". The RESET signal must be kept low during the complete serial programming session. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles duration after SCK has been set to "0". 108 ATmega103(L) 0945G-09/01 ATmega103(L) As an alternative to using the RESET signal, PEN can be held low during Poweron Reset while SCK is set to "0". In this case, only the PEN value at Power-on Reset is important. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that SCK is held low during power-up, the PEN method cannot be used. The device must be powered down in order to commence normal operation when using this method. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin PE0(PDI/RXD). 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a chip erase is performed (must be done to erase the Flash), wait at least (2 x tWD_FLASH), give RESET a positive pulse of at least two XTAL1 cycles duration after SCK has been set to "0", and start over from step 2. 5. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. The next page can be written after tWD_FLASH, i.e., writing 256 bytes takes tWD_FLASH. Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (Please refer to Table 42.) 7. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at serial output PE1(PDO/TXD). 8. At the end of the programming session, RESET can be set high to commence normal operation. 9. Power-off sequence (if needed): Set XTAL1 to "0" (if a crystal is not used). Set RESET to "1". Turn VCC power off. Table 42 shows the actual delays used in this section. Please note: The MISO pin is not high-Z during serial programming. Data Polling for the EEPROM When a new EEPROM byte has been written and is being programmed into the EEPROM, reading the address location being programmed will first give the value P1 (please refer to Table 43) until the auto-erase is finished, and then the value P2. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_EEPROM (please refer to Table 42) before programming the next byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without chip erasing the device. 109 0945G-09/01 Data polling is not implemented for the Flash. Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Symbol tWD_FLASH (Note:) 3.2V 56 ms 9 ms 3.6V 43 ms 7 ms 4.0V 35 ms 6 ms 5.0V 22 ms 4 ms tWD_EEPROM Note: Per page. Table 43. Read Back Value during EEPROM Polling Part/Revision TBD Note: See Errata sheet for latest information. P1 TBD P2 TBD 110 ATmega103(L) 0945G-09/01 ATmega103(L) Table 44. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Load Program Memory Page Write Program Memory Page Read EEPROM Memory Write EEPROM Memory Read Lock Bits Write Lock Bits Read Fuse Bits Write Fuse Bits Read Signature Byte Note: Byte 1 1010 1100 1010 1100 0010 H000 0100 H000 0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0101 0000 1010 1100 0011 0000 Byte 2 0101 0011 100x xxxx aaaa aaaa xxxx xxxx aaaa aaaa xxxx aaaa xxxx aaaa xxxx xxxx 1111 1211 xxxx xxxx 1011 6143 xxxx xxxx Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb xbbb bbbb bxxx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxbb Byte 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx oooo oooo iiii iiii xxxx x21x xxxx xxxx xx5x 6143 xxxx xxxx oooo oooo Operation Enable serial programming while RESET is low. Chip erase EEPROM and Flash. Read H (high or low) data o from program memory at word address a:b. Write H (high or low) data i to program memory page at word address b. Write program memory page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Read Lock bits. "0" = programmed, "1" = unprogrammed. Write Lock bits. Set bits 1,2 = "0" to program Lock bits. Read Fuse bits. "0" = programmed, "1" = unprogrammed. Write Fuse bits. Set bit 6,4,3 = "0" to program, "1" to unprogram. Read signature byte o at address b. a = address high bits b = address low bits H = 0 - Low byte, 1 - High byte o = data out i = data in x = don't care 1 = Lock Bit 1 2 = Lock Bit 2 3 = SUT0 Fuse 4 = SUT1 Fuse 5 = SPIEN Fuse 6 = EESAVE Fuse 111 0945G-09/01 Figure 78. Serial Programming Waveforms SERIAL DATA INPUT PE0(PDI/RXD) SERIAL DATA OUTPUT PE1(PDO/TXD) SERIAL CLOCK INPUT PB1(SCK) SAMPLE MSB LSB MSB LSB 112 ATmega103(L) 0945G-09/01 ATmega103(L) Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -40C to +105C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin except RESET with Respect to Ground ............................... -1.0V to VCC + .5V Voltage on RESET with Respect to Ground ...-1.0V to + 13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND........................................ 400.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40C to 85C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RI/O Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Output Low Voltage Ports A, B, C, D, E (3) Condition Except (XTAL) XTAL Except (XTAL, RESET) XTAL RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V VCC = 6V, Pin Low (absolute value) VCC = 6V, Pin High (absolute value) Min -0.5 -0.5 0.6 VCC(2) 0.7 VCC (2) (2) Typ Max 0.3 VCC (1) (1) Units V V V V V V V V V 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.6 0.5 0.85 VCC Output High Voltage(4) Ports A, B, C, D, E Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pull-up I/O Pin Pull-up 4.3 2.2 8.0 8.0 100 35 500 120 5.0 2.0 40.0 25.0 35.0 A A k k mA mA A A A Active 4 MHz, VCC = 3V Idle 4 MHz, VCC = 3V Power-down , VCC = 3V WDT Enabled Power-down(5), VCC = 3V WDT Disabled Power-save(5), VCC = 3V WDT Disabled (5) ICC Power Supply Current 113 0945G-09/01 DC Characteristics (Continued) TA = -40C to 85C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted) Symbol VACIO IACLK tACPD Notes: 1. 2. 3. Parameter Analog Comp Input Offset V Analog Comp Input Leakage A Condition VCC = 5V VIN = VCC/2 VCC = 5V VIN = VCC/2 -50 Min Typ Max 40 50 Units mV nA 4. 5. 750 Analog Comparator VCC = 2.7V ns 500 Propagation Delay VCC = 4.0V "Max" means the highest value where the pin is guaranteed to be read as low. "Min" means the lowest value where the pin is guaranteed to be read as high. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA. 3] The sum of all IOL, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOL, for ports B0 - B7, should not exceed 100 mA. 5] The sum of all IOL, for ports E0 - E7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. Although each I/O port can source more than the test conditions (3 mA at VCC = 5V, 1.5 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports A0 - A7, ALE, C3 - C7 should not exceed 100 mA. 3] The sum of all IOH, for ports C0 - C2, RD, WR, D0 - D7, XTAL2 should not exceed 100 mA. 4] The sum of all IOH, for ports B0 - B7, should not exceed 100 mA. 5] The sum of all IOH, for ports E0 - E7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Minimum VCC for Power-down is 2V. 114 ATmega103(L) 0945G-09/01 ATmega103(L) External Data Memory Timing Table 45. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State 6 MHz Oscillator Symbol 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL tWHDX tDVWH tWLWH Parameter Oscillator Frequency ALE Pulse Width Address Valid A to ALE Low Address Hold after ALE Low, ST/STD/STS Instructions Address Hold after ALE Low, LD/LDD/LDS Instructions Address Valid C to ALE Low Address Valid to RD Low Address Valid to WR Low ALE Low to WR Low ALE Low to RD Low Data Setup to RD High Read Low to Data Valid Data Hold after RD High RD Pulse Width Data Setup to WR Low Data Hold after WR High Data Valid to WR High WR Pulse Width 0.0 146.7 53.3 0.0 146.7 63.3 48.3 43.3 77.3 15.0 43.3 136.7 215.0 146.7 146.7 70.0 136.7 0.0 1.0 tCLCL - 20.0 0.5 tCLCL - 30.0 0.0 1.0 tCLCL - 20.0 0.5 tCLCL - 20.0(1) (2) Variable Oscillator Min 0.0 0.5 tCLCL - 35.0 (1) Min Max Max 6.0 Unit MHz ns ns ns ns ns ns ns 0.5 tCLCL - 40.0(1) 0.5 tCLCL - 10.0 15.0 0.5 tCLCL - 40.0(1) 1.0 tCLCL - 30.0 1.5 tCLCL - 35.0 186.7 186.7 (1) (2) 1.0 tCLCL - 20.0 0.5 tCLCL - 20.0 70.0 (2) 1.0 tCLCL + 20.0 0.5 tCLCL + 20.0 (2) ns ns ns 1.0 tCLCL - 30.0 ns ns ns ns ns ns ns Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, 1 Cycle Wait State 6 MHz Oscillator Symbol 0 10 12 15 16 Notes: 1/tCLCL tRLDV tRLRH tDVWH tWLWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High WR Pulse Width 313.4 313.4 230.0 303.4 2.0 tCLCL - 20.0 2.0 tCLCL - 20.0 1.5 tCLCL - 20.0 (2) Variable Oscillator Min 0.0 Max 6.0 2.0 tCLCL - 30.0 Unit MHz ns ns ns ns Min Max 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. 115 0945G-09/01 Table 47. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State 4 MHz Oscillator Symbol 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL tWHDX tDVWH tWLWH Parameter Oscillator Frequency ALE Pulse Width Address Valid A to ALE Low Address Hold after ALE Low, ST/STD/STS Instructions Address Hold after ALE Low, LD/LDD/LDS Instructions Address Valid C to ALE Low Address Valid to RD Low Address Valid to WR Low ALE Low to WR Low ALE Low to RD Low Data Setup to RD High Read Low to Data Valid Data Hold after RD High RD Pulse Width Data Setup to WR Low Data Hold after WR High Data Valid to WR High WR Pulse Width 0.0 230.0 90.0 0.0 230.0 100.0 65.0 75.0 125.0 15.0 60.0 205.0 325.0 230.0 105.0 115.0 210.0 0.0 1.0 tCLCL - 20.0 0.5 tCLCL - 35.0(1) 0.0 1.0 tCLCL - 20.0 0.5 tCLCL - 25.0(2) 270.0 145.0 Min Max Variable Oscillator Min 0.0 0.5 tCLCL - 60.0 0.5 tCLCL - 50.0 0.5 tCLCL(2) 15.0 0.5 tCLCL - 65.0(1) 1.0 tCLCL - 45.0 1.5 tCLCL - 65.0 (1) (1) (1) Max 4.0 Unit MHz ns ns ns ns ns ns ns 1.0 tCLCL - 20.0 0.5 tCLCL - 20.0(2) 115.0 1.0 tCLCL + 20.0 0.5 tCLCL + 20.0(2) ns ns ns 1.0 tCLCL - 40.0 ns ns ns ns ns ns ns Table 48. External Data Memory Characteristics, 2.7 - 3.6 Volts, 1 Cycle Wait State 4 MHz Oscillator Symbol 0 10 12 15 1/tCLCL tRLDV tRLRH tDVWH Parameter Oscillator Frequency Read Low to Data Valid RD Pulse Width Data Valid to WR High 480.0 480.0 460.0 2.0 tCLCL - 20.0 2.0 tCLCL - 20.0 (2) Variable Oscillator Min 0.0 Max 4.0 2.0 tCLCL - 40.0 Unit MHz ns ns ns ns Min Max 16 tWLWH WR Pulse Width 350.0 1.5 tCLCL - 25.0 Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. 116 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 79. External RAM Timing T1 0 T2 T3 T4 System Clock O 1 ALE Address [15..8] Prev. Address 4 7 Address 2 13 Address Data 6 3b 16 11 Data 10 8 9 12 Addr. Read 15 Addr. 14 Write Data / Address [7..0] WR Data / Address [7..0] RD Prev. Address 3a Prev. Address Address 5 Note: Clock cycle T3 is only present when external SRAM Wait State is enabled. External Clock Drive Waveforms Figure 80. External Clock Drive Waveforms VIH1 VIL1 Table 49. External Clock Drive Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Note: Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time VCC = 2.7V to 3.6V 0.0 250.0 100.0 100.0 1.6 1.6 4.0 VCC = 4.0V to 5.5V 0.0 167.0 67.0 67.0 0.5 0.5 6.0 Units MHz ns ns ns s s See "External Data Memory Timing" on page 115. for a description of how the duty cycle influences the timing for the external data memory. 117 0945G-09/01 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. All pins on Port F are pulled high externally. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL * VCC * f, where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog timer. Figure 81. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY TA = 25C 50 45 40 Vcc= 5V Vcc= 6V Vcc= 5.5V 35 I cc(mA) 30 25 20 15 10 Vcc= 2.7V Vcc= 3.0V Vcc= 3.6V Vcc= 3.3V Vcc= 4.5V Vcc= 4V 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Frequency (MHz) 118 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 82. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 25 20 TA = 25C TA = 85C I cc(mA) 15 10 5 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 83. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA = 25C 18 16 14 12 I cc(mA) Vcc= 6V Vcc= 5.5V Vcc= 5V Vcc= 4.5V Vcc= 4V 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Vcc= 2.7V Vcc= 3.3V Vcc= 3.0V Vcc= 3.6V Frequency (MHz) 119 0945G-09/01 Figure 84. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 7 6 TA = 85C 5 TA = 25C I cc(mA) 4 3 2 1 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 85. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 70 60 50 40 30 20 10 0 2 2.5 3 3.5 Vcc(V) TA = 70C TA = 85C I cc (A) TA = 45C TA = 25C 4 4.5 5 5.5 6 120 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 86. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 250 200 TA = 85C I cc (A) 150 TA = 25C 100 50 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 87. Power-save Supply Current vs. VCC POWER SAVE SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 80 TA = 85C 70 60 50 I cc (A) 40 30 TA = 25C 20 10 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 121 0945G-09/01 Figure 88. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 0.9 0.8 0.7 0.6 TA = 85C I cc(mA) TA = 25C 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 Vcc(V) 4 4.5 5 5.5 6 Analog comparator offset voltage is measured as absolute offset. Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25C 14 Offset Voltage (mV) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 TA = 85C 4.5 5 Common Mode Voltage (V) 122 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 90. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. Vcc = 2.7V COMMON MODE VOLTAGE 10 TA = 25C 8 Offset Voltage (mV) 6 TA = 85C 4 2 0 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 Figure 91. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25C 60 50 40 ACLK (nA) 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 VIN (V) I 4 4.5 5 5.5 6 6.5 7 123 0945G-09/01 Figure 92. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25C 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 Vcc (V) TA = 85C F RC (KHz) 4.5 5 5.5 6 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 93. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25C 100 TA = 85C 80 OP (A) 60 I 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 124 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 94. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25C 25 TA = 85C 20 OP (A) 15 I 10 5 0 0 0.5 1 1.5 VOP (V) 2 2.5 3 Figure 95. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 60 TA = 85C TA = 25C 50 40 OL (mA) 30 20 10 0 0 0.5 1 1.5 VOL (V) 2 2.5 3 I 125 0945G-09/01 Figure 96. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 18 16 14 12 OH (mA) TA = 25C TA = 85C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 4 4.5 5 Figure 97. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25C I 20 TA = 85C 15 OL (mA) 10 I 5 0 0 0.5 1 VOL (V) 1.5 2 126 ATmega103(L) 0945G-09/01 ATmega103(L) Figure 98. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25C 5 TA = 85C 4 OH (mA) 3 I 2 1 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 99. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25C 2.5 2 Threshold Voltage (V) 1.5 1 0.5 0 2.7 4.0 Vcc 5.0 127 0945G-09/01 Figure 100. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25C 0.18 0.16 Input Hysteresis (V) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 Vcc 5.0 128 ATmega103(L) 0945G-09/01 ATmega103(L) Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $21 ($47) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) $00 ($20) Name SREG SPH SPL XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR ADMUX ADCSR ADCH ADCL PORTE DDRE PINE PINF ACD - ADEN - ADC7 PORTE7 DDE7 PINE7 PINF7 - - ADSC - ADC6 PORTE6 DDE6 PINE6 PINF6 ACO - - - ADC5 PORTE5 DDE5 PINE5 PINF5 RXC RXCIE TXC TXCIE UDRE UDRIE SPIF SPIE WCOL SPE - DORD - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 PORTD7 DDD7 PIND7 - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 PORTD6 DDD6 PIND6 - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 PORTD5 DDD5 PIND5 - - - - - - - PWM2 - COM1A1 ICNC1 - COM1A0 ICES1 - COM1B1 - Bit7 I SP15 SP7 XDIVEN - ISC71 INT7 INTF7 OCIE2 OCF2 SRE - - Bit6 T SP14 SP6 XDIV6 - ISC70 INT6 INTF6 TOIE2 TOV2 SRW - PWM0 Bit5 H SP13 SP5 XDIV5 - ISC61 INT5 INTF5 TICIE1 ICF1 SE - COM01 Bit4 S SP12 SP4 XDIV4 - ISC60 INT4 INTF4 OCIE1A OCF1A SM1 - COM00 Bit3 V SP11 SP3 XDIV3 - ISC51 INT3 - OCIE1B OCF1B SM0 - CTC0 Bit2 N SP10 SP2 XDIV2 - ISC50 INT2 - TOIE1 TOV1 - - CS02 Bit1 Z SP9 SP1 XDIV1 - ISC41 INT1 - OCIE0 OCF0 - EXTRF CS01 Bit0 C SP8 SP0 XDIV0 RAMPZ0 ISC40 INT0 - TOIE0 TOV0 - PORF CS00 Page page 20 page 21 page 21 page 23 page 22 page 30 page 29 page 30 page 31 page 32 page 22 page 28 page 38 page 39 page 40 OCR0UB PWM11 CS11 TCR0UB PWM10 CS10 page 41 page 46 page 47 page 48 page 48 page 48 page 48 page 49 page 49 page 49 page 49 CS21 CS20 page 38 page 39 page 40 WDP1 EEAR9 WDP0 EEAR8 page 52 page 54 page 54 page 54 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 PORTD2 DDD2 PIND2 - CPHA - CHR9 ACIC MUX2 ADPS2 - ADC2 PORTE2 DDE2 PINE2 PINF2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 PORTD1 DDD1 PIND1 - SPR1 - RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1 PORTE1 DDE1 PINE1 PINF1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 PORTD0 DDD0 PIND0 - SPR0 - TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0 PORTE0 DDE0 PINE0 PINF0 page 54 page 81 page 81 page 81 page 83 page 83 page 83 page 89 page 90 page 90 page 90 page 61 page 60 page 59 page 66 page 66 page 67 page 69 page 70 page 75 page 75 page 76 page 76 page 94 page 94 page 94 page 98 WDP2 EEAR10 - CS12 TCN0UB Timer/Counter0 (8-bit) Timer/Counter0 Output Compare Register - COM1B0 - AS0 - CTC1 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte COM21 COM20 CTC2 CS22 Timer/Counter2 (8-bit) Timer/Counter2 Output Compare Register WDTOE - WDE EEAR11 EEPROM Address Register L EEPROM Data Register - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 PORTD4 DDD4 PIND4 - MSTR FE RXEN ACI - ADIF - ADC4 PORTE4 DDE4 PINE4 PINF4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 PORTD3 DDD3 PIND3 - CPOL OR TXEN ACIE - ADIE - ADC3 PORTE3 DDE3 PINE3 PINF3 SPI Data Register UART I/O Data Register UART Baud Rate Register Note: For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical "1" to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 129 0945G-09/01 Instruction Set Summary Mnemonic ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID ELPM MOV LDI Rd, Rr Rd, K Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rdl, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd k Description Add Two Registers Add with Carry Two Registers Add Immediate to Word Subtract Two Registers Subtract Constant from Register Subtract with Carry Two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half-carry Flag Set Branch if Half-carry Flag Cleared Branch if T-flag Set Branch if T-flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Extended Load Program Memory Move between Registers Load Immediate Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if (P(b) = 0) PC PC + 2 or 3 if (P(b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC =PC + k + 1 if (SREG(s) = 0) then PC =PC + k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V = 0) then PC PC + k + 1 if (N V = 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1 R0 (Z + RAMPZ) Rd Rr Rd K Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None I None Z,N,V,C,H Z,N,V,C,H Z,N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None None # Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 3 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS BRANCH INSTRUCTIONS DATA TRANSFER INSTRUCTIONS 130 ATmega103(L) 0945G-09/01 ATmega103(L) Instruction Set Summary (Continued) Mnemonic LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, P P, Rr Rr Rd P, b P, b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Operands Rd, X Rd, X+ Rd, -X Rd, Y Rd, Y+ Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr Description Load Indirect Load Indirect and Post-increment Load Indirect and Pre-decrement Load Indirect Load Indirect and Post-increment Load Indirect and Pre-decrement Load Indirect with Displacement Load Indirect Load Indirect and Post-increment Load Indirect and Pre-decrement Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-increment Store Indirect and Pre-decrement Store Indirect Store Indirect and Post-increment Store Indirect and Pre-decrement Store Indirect with Displacement Store Indirect Store Indirect and Post-increment Store Indirect and Pre-decrement Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left through Carry Rotate Right through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit Load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Two's Complement Overflow Clear Two's Complement Overflow Set T in SREG Clear T in SREG Set Half-carry Flag in SREG Clear Half-carry Flag in SREG No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr. for WD timer) Operation Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z + 1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0) =C, Rd(n+1) Rd(n), C =Rd(7) Rd(7) =C, Rd(n) Rd(n+1), C =Rd(0) Rd(n) Rd(n+1), n = 0..6 Rd(3..0) =Rd(7..4), Rd(7..4) =Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None # Clocks 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT AND BIT-TEST INSTRUCTIONS 131 0945G-09/01 Ordering Information Speed (MHz) 4 Power Supply 2.7 - 3.6V Ordering Code ATmega103L-4AC ATmega103L-4AI 6 4.0 - 5.5V ATmega103-6AC ATMEGA103-6AI Package 64A 64A 64A 64A Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Package Type 64A 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 132 ATmega103(L) 0945G-09/01 ATmega103(L) Packaging Information 64A 64-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP), 14x14mm body, 2.0mm footprint, 0.8mm pitch. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-026 AEB 16.25(0.640) SQ 15.75(0.620) PIN 1 ID PIN 1 0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC 14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.09(0.004) 0~7 1.20 (0.047) MAX 0.75(0.030) 0.45(0.018) *Controlliing dimension: millimeter 0.15(0.006) 0.05(0.002 ) REV. A 04/11/2001 133 0945G-09/01 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Product Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Atmel Heilbronn Theresienstrasse 2 POB 3535 D-74025 Heilbronn, Germany TEL (49) 71 31 67 25 94 FAX (49) 71 31 67 24 23 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 0 2 40 18 18 18 FAX (33) 0 2 40 18 19 60 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and AVR (R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0945G-09/01/xM |
Price & Availability of ATMEGA103-6AI
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |